;
;	clipz8ca.s
;
;	P/ECE Z80 Emulator (高速版)
;
;	CLiP - Common Library for P/ECE
;	Copyright (C) 2001-2005 Naoyuki Sawa
;
;	* Mon Jan 10 19:00:00 JST 2005 Naoyuki Sawa
;	- 作成開始。
;	* Sun Feb 13 03:00:00 JST 2005 Naoyuki Sawa
;	- "ld.ub %rn,[%rn]+"の振る舞いに関するコメント追加。
;	  コードには変更ありません。
;
;#include "clipz8ca.h"
;
;	clipz8ca.h
;
;	P/ECE Z80 Emulator (高速版)
;
;	CLiP - Common Library for P/ECE
;	Copyright (C) 2001-2005 Naoyuki Sawa
;
;	* Mon Jan 10 19:00:00 JST 2005 Naoyuki Sawa
;	- 作成開始。
;

; clipz8ca.s、framz8ca.sにインクルードして使います。

;****************************************************************************
;	Z80CPU構造体
;****************************************************************************

; 通常、レジスタに保持するフィールドは、"_.._"というシンボルにしてあります。
; うっかり読み書きして、保持している値との不整合が発生するのを防ぐためです。
				; /*typedef*/ struct _Z80CPU {
;#define _AF_		 0	; unsigned short af;		/* + 0,2 */
;#define BC		 2	; unsigned short bc;		/* + 2,2 */
;#define DE		 4	; unsigned short de;		/* + 4,2 */
;#define HL		 6	; unsigned short hl;		/* + 6,2 */
;#define AF2		 8	; unsigned short af2;		/* + 8,2 */
;#define BC2		10	; unsigned short bc2;		/* +10,2 */
;#define DE2		12	; unsigned short de2;		/* +12,2 */
;#define HL2		14	; unsigned short hl2;		/* +14,2 */
;#define IX		16	; unsigned short ix;		/* +16,2 */
;#define IY		18	; unsigned short iy;		/* +18,2 */
;#define SP		20	; unsigned short sp;		/* +20,2 */
;#define _PC_		22	; unsigned short pc;		/* +22,2 */
;#define R		24	; unsigned char r;		/* +24,1 */
;#define I		25	; unsigned char i;		/* +25,1 */
;#define IM		26	; unsigned char im;		/* +26,1 */
;#define IFF1		27	; unsigned char iff1;		/* +27,1 */
;#define IFF2		28	; unsigned char iff2;		/* +28,1 */
;#define HALT		29	; unsigned char halt;		/* +29,1 */
;#define PENDING		30	; unsigned char pending;	/* +30,1 */
;#define PENDING_NO	31	; unsigned char pending_no;	/* +31,1 */
;#define _CYCLE_		32	; cycle;			/* +32,4 */
;#define IN		36	; Z80CPUIN* in;			/* +36,4 */
;#define OUT		40	; Z80CPUOUT* out;		/* +40,4 */
;#define SIZEOF_Z80CPU	44	; } /*Z80CPU*/;			/* =44   */

;#define _F_		 0
;#define _A_		 1
;#define C		 2
;#define B		 3
;#define E		 4
;#define D		 5
;#define L		 6
;#define H		 7
;#define IXL		16
;#define IXH		17
;#define IYL		18
;#define IYH		19

;****************************************************************************
;	レジスタ割り当て
;****************************************************************************

;#define A		r0	; Aレジスタを保持。              [31:8]は常に0。
;#define F		r1	; Fレジスタを(NHCPZS)形式で保持。[31:6]は常に0。
;#define PC		r2	; PCレジスタを(&z80mem[PC])形式で保持。
;#define CYCLE		r3	; 残りCycle数を保持。
;#define CPU		r4	; z80cpuの先頭アドレスに固定。
;#define MEM		r5	; z80memの先頭アドレスに固定。
;#define s0		r6	; 命令ルーチンにて使用。サブルーチンは値を維持する。
;#define s1		r7	; 命令ルーチンにて使用。サブルーチンは値を維持する。
;			r8	; ゼロレジスタ。      (P/ECE仕様)
;			r9	; スクラッチレジスタ。(S1C33仕様)
;#define a0		r10	; 命令ルーチンからサブルーチンへの第一引数／サブルーチンからの戻り値。戻り値が無い場合、サブルーチンは値を破壊する。
;#define a1		r11	; 命令ルーチンからサブルーチンへの第二引数／サブルーチンからの戻り値。戻り値が無い場合、サブルーチンは値を破壊する。
;#define t0		r12	; 命令ルーチンおよびサブルーチンにて使用。サブルーチンは値を破壊する。
;#define t1		r13	; 命令ルーチンおよびサブルーチンにて使用。サブルーチンは値を破壊する。
;#define t2		r14	; 命令ルーチンおよびサブルーチンにて使用。サブルーチンは値を破壊する。
;#define t3		r15	; 命令ルーチンおよびサブルーチンにて使用。サブルーチンは値を破壊する。

;****************************************************************************
;	フラグビット定義
;****************************************************************************

; * %rFレジスタのフラグビットです。すなわち、F(NHCPZS)の並びです。
; - アルファベット2文字のフラグ名称は、"Undocumented Z80"から借用しました。
;#define SF	0x01
;#define ZF	0x02
;#define PF	0x04
;#define CF	0x08
;#define HF	0x10
;#define NF	0x20

;****************************************************************************
;	8-Bit Load Group
;****************************************************************************

;#define CYCLE_LD_A_n		7
;#define CYCLE_LD_A_A		4
;#define CYCLE_LD_A_B		4
;#define CYCLE_LD_A_C		4
;#define CYCLE_LD_A_D		4
;#define CYCLE_LD_A_E		4
;#define CYCLE_LD_A_H		4
;#define CYCLE_LD_A_L		4
;#define CYCLE_LD_A_IXH		8
;#define CYCLE_LD_A_IXL		8
;#define CYCLE_LD_A_IYH		8
;#define CYCLE_LD_A_IYL		8
;#define CYCLE_LD_B_n		7
;#define CYCLE_LD_B_A		4
;#define CYCLE_LD_B_B		4
;#define CYCLE_LD_B_C		4
;#define CYCLE_LD_B_D		4
;#define CYCLE_LD_B_E		4
;#define CYCLE_LD_B_H		4
;#define CYCLE_LD_B_L		4
;#define CYCLE_LD_B_IXH		8
;#define CYCLE_LD_B_IXL		8
;#define CYCLE_LD_B_IYH		8
;#define CYCLE_LD_B_IYL		8
;#define CYCLE_LD_C_n		7
;#define CYCLE_LD_C_A		4
;#define CYCLE_LD_C_B		4
;#define CYCLE_LD_C_C		4
;#define CYCLE_LD_C_D		4
;#define CYCLE_LD_C_E		4
;#define CYCLE_LD_C_H		4
;#define CYCLE_LD_C_L		4
;#define CYCLE_LD_C_IXH		8
;#define CYCLE_LD_C_IXL		8
;#define CYCLE_LD_C_IYH		8
;#define CYCLE_LD_C_IYL		8
;#define CYCLE_LD_D_n		7
;#define CYCLE_LD_D_A		4
;#define CYCLE_LD_D_B		4
;#define CYCLE_LD_D_C		4
;#define CYCLE_LD_D_D		4
;#define CYCLE_LD_D_E		4
;#define CYCLE_LD_D_H		4
;#define CYCLE_LD_D_L		4
;#define CYCLE_LD_D_IXH		8
;#define CYCLE_LD_D_IXL		8
;#define CYCLE_LD_D_IYH		8
;#define CYCLE_LD_D_IYL		8
;#define CYCLE_LD_E_n		7
;#define CYCLE_LD_E_A		4
;#define CYCLE_LD_E_B		4
;#define CYCLE_LD_E_C		4
;#define CYCLE_LD_E_D		4
;#define CYCLE_LD_E_E		4
;#define CYCLE_LD_E_H		4
;#define CYCLE_LD_E_L		4
;#define CYCLE_LD_E_IXH		8
;#define CYCLE_LD_E_IXL		8
;#define CYCLE_LD_E_IYH		8
;#define CYCLE_LD_E_IYL		8
;#define CYCLE_LD_H_n		7
;#define CYCLE_LD_H_A		4
;#define CYCLE_LD_H_B		4
;#define CYCLE_LD_H_C		4
;#define CYCLE_LD_H_D		4
;#define CYCLE_LD_H_E		4
;#define CYCLE_LD_H_H		4
;#define CYCLE_LD_H_L		4
;#define CYCLE_LD_L_n		7
;#define CYCLE_LD_L_A		4
;#define CYCLE_LD_L_B		4
;#define CYCLE_LD_L_C		4
;#define CYCLE_LD_L_D		4
;#define CYCLE_LD_L_E		4
;#define CYCLE_LD_L_H		4
;#define CYCLE_LD_L_L		4
;#define CYCLE_LD_IXH_n		11
;#define CYCLE_LD_IXH_A		8
;#define CYCLE_LD_IXH_B		8
;#define CYCLE_LD_IXH_C		8
;#define CYCLE_LD_IXH_D		8
;#define CYCLE_LD_IXH_E		8
;#define CYCLE_LD_IXH_IXH	8
;#define CYCLE_LD_IXH_IXL	8
;#define CYCLE_LD_IXL_n		11
;#define CYCLE_LD_IXL_A		8
;#define CYCLE_LD_IXL_B		8
;#define CYCLE_LD_IXL_C		8
;#define CYCLE_LD_IXL_D		8
;#define CYCLE_LD_IXL_E		8
;#define CYCLE_LD_IXL_IXH	8
;#define CYCLE_LD_IXL_IXL	8
;#define CYCLE_LD_IYH_n		11
;#define CYCLE_LD_IYH_A		8
;#define CYCLE_LD_IYH_B		8
;#define CYCLE_LD_IYH_C		8
;#define CYCLE_LD_IYH_D		8
;#define CYCLE_LD_IYH_E		8
;#define CYCLE_LD_IYH_IYH	8
;#define CYCLE_LD_IYH_IYL	8
;#define CYCLE_LD_IYL_n		11
;#define CYCLE_LD_IYL_A		8
;#define CYCLE_LD_IYL_B		8
;#define CYCLE_LD_IYL_C		8
;#define CYCLE_LD_IYL_D		8
;#define CYCLE_LD_IYL_E		8
;#define CYCLE_LD_IYL_IYH	8
;#define CYCLE_LD_IYL_IYL	8

;#define CYCLE_LD_A_IlmI		13
;#define CYCLE_LD_A_IBCI		7
;#define CYCLE_LD_A_IDEI		7
;#define CYCLE_LD_A_IHLI		7
;#define CYCLE_LD_B_IHLI		7
;#define CYCLE_LD_C_IHLI		7
;#define CYCLE_LD_D_IHLI		7
;#define CYCLE_LD_E_IHLI		7
;#define CYCLE_LD_H_IHLI		7
;#define CYCLE_LD_L_IHLI		7
;#define CYCLE_LD_A_IIX_dI	19
;#define CYCLE_LD_B_IIX_dI	19
;#define CYCLE_LD_C_IIX_dI	19
;#define CYCLE_LD_D_IIX_dI	19
;#define CYCLE_LD_E_IIX_dI	19
;#define CYCLE_LD_H_IIX_dI	19
;#define CYCLE_LD_L_IIX_dI	19
;#define CYCLE_LD_A_IIY_dI	19
;#define CYCLE_LD_B_IIY_dI	19
;#define CYCLE_LD_C_IIY_dI	19
;#define CYCLE_LD_D_IIY_dI	19
;#define CYCLE_LD_E_IIY_dI	19
;#define CYCLE_LD_H_IIY_dI	19
;#define CYCLE_LD_L_IIY_dI	19

;#define CYCLE_LD_IlmI_A		13
;#define CYCLE_LD_IHLI_n		10
;#define CYCLE_LD_IBCI_A		7
;#define CYCLE_LD_IDEI_A		7
;#define CYCLE_LD_IHLI_A		7
;#define CYCLE_LD_IHLI_B		7
;#define CYCLE_LD_IHLI_C		7
;#define CYCLE_LD_IHLI_D		7
;#define CYCLE_LD_IHLI_E		7
;#define CYCLE_LD_IHLI_H		7
;#define CYCLE_LD_IHLI_L		7
;#define CYCLE_LD_IIX_dI_n	19
;#define CYCLE_LD_IIY_dI_n	19
;#define CYCLE_LD_IIX_dI_A	19
;#define CYCLE_LD_IIX_dI_B	19
;#define CYCLE_LD_IIX_dI_C	19
;#define CYCLE_LD_IIX_dI_D	19
;#define CYCLE_LD_IIX_dI_E	19
;#define CYCLE_LD_IIX_dI_H	19
;#define CYCLE_LD_IIX_dI_L	19
;#define CYCLE_LD_IIY_dI_A	19
;#define CYCLE_LD_IIY_dI_B	19
;#define CYCLE_LD_IIY_dI_C	19
;#define CYCLE_LD_IIY_dI_D	19
;#define CYCLE_LD_IIY_dI_E	19
;#define CYCLE_LD_IIY_dI_H	19
;#define CYCLE_LD_IIY_dI_L	19

;#define CYCLE_LD_A_I		9
;#define CYCLE_LD_A_R		9
;#define CYCLE_LD_I_A		9
;#define CYCLE_LD_R_A		9

;****************************************************************************
;	16-Bit Load Group
;****************************************************************************

;#define CYCLE_LD_SP_HL		6
;#define CYCLE_LD_SP_IX		10
;#define CYCLE_LD_SP_IY		10

;#define CYCLE_LD_BC_lm		10
;#define CYCLE_LD_DE_lm		10
;#define CYCLE_LD_HL_lm		10
;#define CYCLE_LD_SP_lm		10
;#define CYCLE_LD_IX_lm		14
;#define CYCLE_LD_IY_lm		14

;#define CYCLE_LD_BC_IlmI	20
;#define CYCLE_LD_DE_IlmI	20
;#define CYCLE_LD_HL_IlmI	16
;#define CYCLE_LD_SP_IlmI	20
;#define CYCLE_LD_IX_IlmI	20
;#define CYCLE_LD_IY_IlmI	20

;#define CYCLE_LD_IlmI_BC	20
;#define CYCLE_LD_IlmI_DE	20
;#define CYCLE_LD_IlmI_HL	16
;#define CYCLE_LD_IlmI_SP	20
;#define CYCLE_LD_IlmI_IX	20
;#define CYCLE_LD_IlmI_IY	20

;#define CYCLE_POP_AF		10
;#define CYCLE_POP_BC		10
;#define CYCLE_POP_DE		10
;#define CYCLE_POP_HL		10
;#define CYCLE_POP_IX		14
;#define CYCLE_POP_IY		14

;#define CYCLE_PUSH_AF		11
;#define CYCLE_PUSH_BC		11
;#define CYCLE_PUSH_DE		11
;#define CYCLE_PUSH_HL		11
;#define CYCLE_PUSH_IX		15
;#define CYCLE_PUSH_IY		15

;****************************************************************************
;	Exchange, Block Transfer, and Search Group
;****************************************************************************

;#define CYCLE_EX_ISPI_HL	19
;#define CYCLE_EX_ISPI_IX	23
;#define CYCLE_EX_ISPI_IY	23
;#define CYCLE_EX_AF_AF2		4
;#define CYCLE_EX_DE_HL		4
;#define CYCLE_EXX		4

;#define CYCLE_LDI		16
;#define CYCLE_LDIR		16
;#define CYCLE_LDD		16
;#define CYCLE_LDDR		16

;#define CYCLE_CPI		16
;#define CYCLE_CPIR		16
;#define CYCLE_CPD		16
;#define CYCLE_CPDR		16

;****************************************************************************
;	8-Bit Arithmetic Group
;****************************************************************************

;#define CYCLE_ADD_A_n		7
;#define CYCLE_ADD_A_A		4
;#define CYCLE_ADD_A_B		4
;#define CYCLE_ADD_A_C		4
;#define CYCLE_ADD_A_D		4
;#define CYCLE_ADD_A_E		4
;#define CYCLE_ADD_A_H		4
;#define CYCLE_ADD_A_L		4
;#define CYCLE_ADD_A_IXH		8
;#define CYCLE_ADD_A_IXL		8
;#define CYCLE_ADD_A_IYH		8
;#define CYCLE_ADD_A_IYL		8
;#define CYCLE_ADD_A_IHLI	7
;#define CYCLE_ADD_A_IIX_dI	19
;#define CYCLE_ADD_A_IIY_dI	19

;#define CYCLE_ADC_A_n		7
;#define CYCLE_ADC_A_A		4
;#define CYCLE_ADC_A_B		4
;#define CYCLE_ADC_A_C		4
;#define CYCLE_ADC_A_D		4
;#define CYCLE_ADC_A_E		4
;#define CYCLE_ADC_A_H		4
;#define CYCLE_ADC_A_L		4
;#define CYCLE_ADC_A_IXH		8
;#define CYCLE_ADC_A_IXL		8
;#define CYCLE_ADC_A_IYH		8
;#define CYCLE_ADC_A_IYL		8
;#define CYCLE_ADC_A_IHLI	7
;#define CYCLE_ADC_A_IIX_dI	19
;#define CYCLE_ADC_A_IIY_dI	19

;#define CYCLE_SUB_n		7
;#define CYCLE_SUB_A		4
;#define CYCLE_SUB_B		4
;#define CYCLE_SUB_C		4
;#define CYCLE_SUB_D		4
;#define CYCLE_SUB_E		4
;#define CYCLE_SUB_H		4
;#define CYCLE_SUB_L		4
;#define CYCLE_SUB_IXH		8
;#define CYCLE_SUB_IXL		8
;#define CYCLE_SUB_IYH		8
;#define CYCLE_SUB_IYL		8
;#define CYCLE_SUB_IHLI		7
;#define CYCLE_SUB_IIX_dI	19
;#define CYCLE_SUB_IIY_dI	19

;#define CYCLE_SBC_A_n		7
;#define CYCLE_SBC_A_A		4
;#define CYCLE_SBC_A_B		4
;#define CYCLE_SBC_A_C		4
;#define CYCLE_SBC_A_D		4
;#define CYCLE_SBC_A_E		4
;#define CYCLE_SBC_A_H		4
;#define CYCLE_SBC_A_L		4
;#define CYCLE_SBC_A_IXH		8
;#define CYCLE_SBC_A_IXL		8
;#define CYCLE_SBC_A_IYH		8
;#define CYCLE_SBC_A_IYL		8
;#define CYCLE_SBC_A_IHLI	7
;#define CYCLE_SBC_A_IIX_dI	19
;#define CYCLE_SBC_A_IIY_dI	19

;#define CYCLE_AND_n		7
;#define CYCLE_AND_A		4
;#define CYCLE_AND_B		4
;#define CYCLE_AND_C		4
;#define CYCLE_AND_D		4
;#define CYCLE_AND_E		4
;#define CYCLE_AND_H		4
;#define CYCLE_AND_L		4
;#define CYCLE_AND_IXH		8
;#define CYCLE_AND_IXL		8
;#define CYCLE_AND_IYH		8
;#define CYCLE_AND_IYL		8
;#define CYCLE_AND_IHLI		7
;#define CYCLE_AND_IIX_dI	19
;#define CYCLE_AND_IIY_dI	19

;#define CYCLE_OR_n		7
;#define CYCLE_OR_A		4
;#define CYCLE_OR_B		4
;#define CYCLE_OR_C		4
;#define CYCLE_OR_D		4
;#define CYCLE_OR_E		4
;#define CYCLE_OR_H		4
;#define CYCLE_OR_L		4
;#define CYCLE_OR_IXH		8
;#define CYCLE_OR_IXL		8
;#define CYCLE_OR_IYH		8
;#define CYCLE_OR_IYL		8
;#define CYCLE_OR_IHLI		7
;#define CYCLE_OR_IIX_dI		19
;#define CYCLE_OR_IIY_dI		19

;#define CYCLE_XOR_n		7
;#define CYCLE_XOR_A		4
;#define CYCLE_XOR_B		4
;#define CYCLE_XOR_C		4
;#define CYCLE_XOR_D		4
;#define CYCLE_XOR_E		4
;#define CYCLE_XOR_H		4
;#define CYCLE_XOR_L		4
;#define CYCLE_XOR_IXH		8
;#define CYCLE_XOR_IXL		8
;#define CYCLE_XOR_IYH		8
;#define CYCLE_XOR_IYL		8
;#define CYCLE_XOR_IHLI		7
;#define CYCLE_XOR_IIX_dI	19
;#define CYCLE_XOR_IIY_dI	19

;#define CYCLE_CP_n		7
;#define CYCLE_CP_A		4
;#define CYCLE_CP_B		4
;#define CYCLE_CP_C		4
;#define CYCLE_CP_D		4
;#define CYCLE_CP_E		4
;#define CYCLE_CP_H		4
;#define CYCLE_CP_L		4
;#define CYCLE_CP_IXH		8
;#define CYCLE_CP_IXL		8
;#define CYCLE_CP_IYH		8
;#define CYCLE_CP_IYL		8
;#define CYCLE_CP_IHLI		7
;#define CYCLE_CP_IIX_dI		19
;#define CYCLE_CP_IIY_dI		19

;#define CYCLE_INC_A		4
;#define CYCLE_INC_B		4
;#define CYCLE_INC_C		4
;#define CYCLE_INC_D		4
;#define CYCLE_INC_E		4
;#define CYCLE_INC_H		4
;#define CYCLE_INC_L		4
;#define CYCLE_INC_IXH		8
;#define CYCLE_INC_IXL		8
;#define CYCLE_INC_IYH		8
;#define CYCLE_INC_IYL		8
;#define CYCLE_INC_IHLI		11
;#define CYCLE_INC_IIX_dI	23
;#define CYCLE_INC_IIY_dI	23

;#define CYCLE_DEC_A		4
;#define CYCLE_DEC_B		4
;#define CYCLE_DEC_C		4
;#define CYCLE_DEC_D		4
;#define CYCLE_DEC_E		4
;#define CYCLE_DEC_H		4
;#define CYCLE_DEC_L		4
;#define CYCLE_DEC_IXH		8
;#define CYCLE_DEC_IXL		8
;#define CYCLE_DEC_IYH		8
;#define CYCLE_DEC_IYL		8
;#define CYCLE_DEC_IHLI		11
;#define CYCLE_DEC_IIX_dI	23
;#define CYCLE_DEC_IIY_dI	23

;****************************************************************************
;	General-Purpose Arithmetic and CPU Control Group
;****************************************************************************

;#define CYCLE_DAA		4
;#define CYCLE_CPL		4
;#define CYCLE_NEG		8
;#define CYCLE_CCF		4
;#define CYCLE_SCF		4
;#define CYCLE_NOP		4
;#define CYCLE_HALT		4
;#define CYCLE_DI		4
;#define CYCLE_EI		4
;#define CYCLE_IM_0		8
;#define CYCLE_IM_1		8
;#define CYCLE_IM_2		8

;****************************************************************************
;	16-Bit Arithmetic Group
;****************************************************************************

;#define CYCLE_ADD_HL_BC		11
;#define CYCLE_ADD_HL_DE		11
;#define CYCLE_ADD_HL_HL		11
;#define CYCLE_ADD_HL_SP		11
;#define CYCLE_ADD_IX_BC		15
;#define CYCLE_ADD_IX_DE		15
;#define CYCLE_ADD_IX_IX		15
;#define CYCLE_ADD_IX_SP		15
;#define CYCLE_ADD_IY_BC		15
;#define CYCLE_ADD_IY_DE		15
;#define CYCLE_ADD_IY_IY		15
;#define CYCLE_ADD_IY_SP		15

;#define CYCLE_ADC_HL_BC		15
;#define CYCLE_ADC_HL_DE		15
;#define CYCLE_ADC_HL_HL		15
;#define CYCLE_ADC_HL_SP		15

;#define CYCLE_SBC_HL_BC		15
;#define CYCLE_SBC_HL_DE		15
;#define CYCLE_SBC_HL_HL		15
;#define CYCLE_SBC_HL_SP		15

;#define CYCLE_INC_BC		6
;#define CYCLE_INC_DE		6
;#define CYCLE_INC_HL		6
;#define CYCLE_INC_SP		6
;#define CYCLE_INC_IX		10
;#define CYCLE_INC_IY		10

;#define CYCLE_DEC_BC		6
;#define CYCLE_DEC_DE		6
;#define CYCLE_DEC_HL		6
;#define CYCLE_DEC_SP		6
;#define CYCLE_DEC_IX		10
;#define CYCLE_DEC_IY		10

;****************************************************************************
;	Rotate and Shift Group
;****************************************************************************

;#define CYCLE_RLA		4
;#define CYCLE_RLCA		4
;#define CYCLE_RRA		4
;#define CYCLE_RRCA		4

;#define CYCLE_RL_A		8
;#define CYCLE_RL_B		8
;#define CYCLE_RL_C		8
;#define CYCLE_RL_D		8
;#define CYCLE_RL_E		8
;#define CYCLE_RL_H		8
;#define CYCLE_RL_L		8
;#define CYCLE_RL_IHLI		15
;#define CYCLE_RL_IaddrI		23

;#define CYCLE_RLC_A		8
;#define CYCLE_RLC_B		8
;#define CYCLE_RLC_C		8
;#define CYCLE_RLC_D		8
;#define CYCLE_RLC_E		8
;#define CYCLE_RLC_H		8
;#define CYCLE_RLC_L		8
;#define CYCLE_RLC_IHLI		15
;#define CYCLE_RLC_IaddrI	23

;#define CYCLE_RR_A		8
;#define CYCLE_RR_B		8
;#define CYCLE_RR_C		8
;#define CYCLE_RR_D		8
;#define CYCLE_RR_E		8
;#define CYCLE_RR_H		8
;#define CYCLE_RR_L		8
;#define CYCLE_RR_IHLI		15
;#define CYCLE_RR_IaddrI		23

;#define CYCLE_RRC_A		8
;#define CYCLE_RRC_B		8
;#define CYCLE_RRC_C		8
;#define CYCLE_RRC_D		8
;#define CYCLE_RRC_E		8
;#define CYCLE_RRC_H		8
;#define CYCLE_RRC_L		8
;#define CYCLE_RRC_IHLI		15
;#define CYCLE_RRC_IaddrI	23

;#define CYCLE_SLA_A		8
;#define CYCLE_SLA_B		8
;#define CYCLE_SLA_C		8
;#define CYCLE_SLA_D		8
;#define CYCLE_SLA_E		8
;#define CYCLE_SLA_H		8
;#define CYCLE_SLA_L		8
;#define CYCLE_SLA_IHLI		15
;#define CYCLE_SLA_IaddrI	23

;#define CYCLE_SRA_A		8
;#define CYCLE_SRA_B		8
;#define CYCLE_SRA_C		8
;#define CYCLE_SRA_D		8
;#define CYCLE_SRA_E		8
;#define CYCLE_SRA_H		8
;#define CYCLE_SRA_L		8
;#define CYCLE_SRA_IHLI		15
;#define CYCLE_SRA_IaddrI	23

;#define CYCLE_SRL_A		8
;#define CYCLE_SRL_B		8
;#define CYCLE_SRL_C		8
;#define CYCLE_SRL_D		8
;#define CYCLE_SRL_E		8
;#define CYCLE_SRL_H		8
;#define CYCLE_SRL_L		8
;#define CYCLE_SRL_IHLI		15
;#define CYCLE_SRL_IaddrI	23

;#define CYCLE_RLD		18
;#define CYCLE_RRD		18

;****************************************************************************
;	Bit Set, Reset, and Test Group
;****************************************************************************

;#define CYCLE_BIT_0_A		8
;#define CYCLE_BIT_0_B		8
;#define CYCLE_BIT_0_C		8
;#define CYCLE_BIT_0_D		8
;#define CYCLE_BIT_0_E		8
;#define CYCLE_BIT_0_H		8
;#define CYCLE_BIT_0_L		8
;#define CYCLE_BIT_0_IHLI	12
;#define CYCLE_BIT_0_IaddrI	20
;#define CYCLE_BIT_1_A		8
;#define CYCLE_BIT_1_B		8
;#define CYCLE_BIT_1_C		8
;#define CYCLE_BIT_1_D		8
;#define CYCLE_BIT_1_E		8
;#define CYCLE_BIT_1_H		8
;#define CYCLE_BIT_1_L		8
;#define CYCLE_BIT_1_IHLI	12
;#define CYCLE_BIT_1_IaddrI	20
;#define CYCLE_BIT_2_A		8
;#define CYCLE_BIT_2_B		8
;#define CYCLE_BIT_2_C		8
;#define CYCLE_BIT_2_D		8
;#define CYCLE_BIT_2_E		8
;#define CYCLE_BIT_2_H		8
;#define CYCLE_BIT_2_L		8
;#define CYCLE_BIT_2_IHLI	12
;#define CYCLE_BIT_2_IaddrI	20
;#define CYCLE_BIT_3_A		8
;#define CYCLE_BIT_3_B		8
;#define CYCLE_BIT_3_C		8
;#define CYCLE_BIT_3_D		8
;#define CYCLE_BIT_3_E		8
;#define CYCLE_BIT_3_H		8
;#define CYCLE_BIT_3_L		8
;#define CYCLE_BIT_3_IHLI	12
;#define CYCLE_BIT_3_IaddrI	20
;#define CYCLE_BIT_4_A		8
;#define CYCLE_BIT_4_B		8
;#define CYCLE_BIT_4_C		8
;#define CYCLE_BIT_4_D		8
;#define CYCLE_BIT_4_E		8
;#define CYCLE_BIT_4_H		8
;#define CYCLE_BIT_4_L		8
;#define CYCLE_BIT_4_IHLI	12
;#define CYCLE_BIT_4_IaddrI	20
;#define CYCLE_BIT_5_A		8
;#define CYCLE_BIT_5_B		8
;#define CYCLE_BIT_5_C		8
;#define CYCLE_BIT_5_D		8
;#define CYCLE_BIT_5_E		8
;#define CYCLE_BIT_5_H		8
;#define CYCLE_BIT_5_L		8
;#define CYCLE_BIT_5_IHLI	12
;#define CYCLE_BIT_5_IaddrI	20
;#define CYCLE_BIT_6_A		8
;#define CYCLE_BIT_6_B		8
;#define CYCLE_BIT_6_C		8
;#define CYCLE_BIT_6_D		8
;#define CYCLE_BIT_6_E		8
;#define CYCLE_BIT_6_H		8
;#define CYCLE_BIT_6_L		8
;#define CYCLE_BIT_6_IHLI	12
;#define CYCLE_BIT_6_IaddrI	20
;#define CYCLE_BIT_7_A		8
;#define CYCLE_BIT_7_B		8
;#define CYCLE_BIT_7_C		8
;#define CYCLE_BIT_7_D		8
;#define CYCLE_BIT_7_E		8
;#define CYCLE_BIT_7_H		8
;#define CYCLE_BIT_7_L		8
;#define CYCLE_BIT_7_IHLI	12
;#define CYCLE_BIT_7_IaddrI	20

;#define CYCLE_SET_0_A		8
;#define CYCLE_SET_0_B		8
;#define CYCLE_SET_0_C		8
;#define CYCLE_SET_0_D		8
;#define CYCLE_SET_0_E		8
;#define CYCLE_SET_0_H		8
;#define CYCLE_SET_0_L		8
;#define CYCLE_SET_0_IHLI	15
;#define CYCLE_SET_0_IaddrI	23
;#define CYCLE_SET_1_A		8
;#define CYCLE_SET_1_B		8
;#define CYCLE_SET_1_C		8
;#define CYCLE_SET_1_D		8
;#define CYCLE_SET_1_E		8
;#define CYCLE_SET_1_H		8
;#define CYCLE_SET_1_L		8
;#define CYCLE_SET_1_IHLI	15
;#define CYCLE_SET_1_IaddrI	23
;#define CYCLE_SET_2_A		8
;#define CYCLE_SET_2_B		8
;#define CYCLE_SET_2_C		8
;#define CYCLE_SET_2_D		8
;#define CYCLE_SET_2_E		8
;#define CYCLE_SET_2_H		8
;#define CYCLE_SET_2_L		8
;#define CYCLE_SET_2_IHLI	15
;#define CYCLE_SET_2_IaddrI	23
;#define CYCLE_SET_3_A		8
;#define CYCLE_SET_3_B		8
;#define CYCLE_SET_3_C		8
;#define CYCLE_SET_3_D		8
;#define CYCLE_SET_3_E		8
;#define CYCLE_SET_3_H		8
;#define CYCLE_SET_3_L		8
;#define CYCLE_SET_3_IHLI	15
;#define CYCLE_SET_3_IaddrI	23
;#define CYCLE_SET_4_A		8
;#define CYCLE_SET_4_B		8
;#define CYCLE_SET_4_C		8
;#define CYCLE_SET_4_D		8
;#define CYCLE_SET_4_E		8
;#define CYCLE_SET_4_H		8
;#define CYCLE_SET_4_L		8
;#define CYCLE_SET_4_IHLI	15
;#define CYCLE_SET_4_IaddrI	23
;#define CYCLE_SET_5_A		8
;#define CYCLE_SET_5_B		8
;#define CYCLE_SET_5_C		8
;#define CYCLE_SET_5_D		8
;#define CYCLE_SET_5_E		8
;#define CYCLE_SET_5_H		8
;#define CYCLE_SET_5_L		8
;#define CYCLE_SET_5_IHLI	15
;#define CYCLE_SET_5_IaddrI	23
;#define CYCLE_SET_6_A		8
;#define CYCLE_SET_6_B		8
;#define CYCLE_SET_6_C		8
;#define CYCLE_SET_6_D		8
;#define CYCLE_SET_6_E		8
;#define CYCLE_SET_6_H		8
;#define CYCLE_SET_6_L		8
;#define CYCLE_SET_6_IHLI	15
;#define CYCLE_SET_6_IaddrI	23
;#define CYCLE_SET_7_A		8
;#define CYCLE_SET_7_B		8
;#define CYCLE_SET_7_C		8
;#define CYCLE_SET_7_D		8
;#define CYCLE_SET_7_E		8
;#define CYCLE_SET_7_H		8
;#define CYCLE_SET_7_L		8
;#define CYCLE_SET_7_IHLI	15
;#define CYCLE_SET_7_IaddrI	23

;#define CYCLE_RES_0_A		8
;#define CYCLE_RES_0_B		8
;#define CYCLE_RES_0_C		8
;#define CYCLE_RES_0_D		8
;#define CYCLE_RES_0_E		8
;#define CYCLE_RES_0_H		8
;#define CYCLE_RES_0_L		8
;#define CYCLE_RES_0_IHLI	15
;#define CYCLE_RES_0_IaddrI	23
;#define CYCLE_RES_1_A		8
;#define CYCLE_RES_1_B		8
;#define CYCLE_RES_1_C		8
;#define CYCLE_RES_1_D		8
;#define CYCLE_RES_1_E		8
;#define CYCLE_RES_1_H		8
;#define CYCLE_RES_1_L		8
;#define CYCLE_RES_1_IHLI	15
;#define CYCLE_RES_1_IaddrI	23
;#define CYCLE_RES_2_A		8
;#define CYCLE_RES_2_B		8
;#define CYCLE_RES_2_C		8
;#define CYCLE_RES_2_D		8
;#define CYCLE_RES_2_E		8
;#define CYCLE_RES_2_H		8
;#define CYCLE_RES_2_L		8
;#define CYCLE_RES_2_IHLI	15
;#define CYCLE_RES_2_IaddrI	23
;#define CYCLE_RES_3_A		8
;#define CYCLE_RES_3_B		8
;#define CYCLE_RES_3_C		8
;#define CYCLE_RES_3_D		8
;#define CYCLE_RES_3_E		8
;#define CYCLE_RES_3_H		8
;#define CYCLE_RES_3_L		8
;#define CYCLE_RES_3_IHLI	15
;#define CYCLE_RES_3_IaddrI	23
;#define CYCLE_RES_4_A		8
;#define CYCLE_RES_4_B		8
;#define CYCLE_RES_4_C		8
;#define CYCLE_RES_4_D		8
;#define CYCLE_RES_4_E		8
;#define CYCLE_RES_4_H		8
;#define CYCLE_RES_4_L		8
;#define CYCLE_RES_4_IHLI	15
;#define CYCLE_RES_4_IaddrI	23
;#define CYCLE_RES_5_A		8
;#define CYCLE_RES_5_B		8
;#define CYCLE_RES_5_C		8
;#define CYCLE_RES_5_D		8
;#define CYCLE_RES_5_E		8
;#define CYCLE_RES_5_H		8
;#define CYCLE_RES_5_L		8
;#define CYCLE_RES_5_IHLI	15
;#define CYCLE_RES_5_IaddrI	23
;#define CYCLE_RES_6_A		8
;#define CYCLE_RES_6_B		8
;#define CYCLE_RES_6_C		8
;#define CYCLE_RES_6_D		8
;#define CYCLE_RES_6_E		8
;#define CYCLE_RES_6_H		8
;#define CYCLE_RES_6_L		8
;#define CYCLE_RES_6_IHLI	15
;#define CYCLE_RES_6_IaddrI	23
;#define CYCLE_RES_7_A		8
;#define CYCLE_RES_7_B		8
;#define CYCLE_RES_7_C		8
;#define CYCLE_RES_7_D		8
;#define CYCLE_RES_7_E		8
;#define CYCLE_RES_7_H		8
;#define CYCLE_RES_7_L		8
;#define CYCLE_RES_7_IHLI	15
;#define CYCLE_RES_7_IaddrI	23

;****************************************************************************
;	Jump Group
;****************************************************************************

;#define CYCLE_JP_IHLI		4
;#define CYCLE_JP_IIXI		8
;#define CYCLE_JP_IIYI		8

;#define CYCLE_JP_lm		10
;#define CYCLE_JP_Z_lm		10
;#define CYCLE_JP_NZ_lm		10
;#define CYCLE_JP_C_lm		10
;#define CYCLE_JP_NC_lm		10
;#define CYCLE_JP_PE_lm		10
;#define CYCLE_JP_PO_lm		10
;#define CYCLE_JP_M_lm		10
;#define CYCLE_JP_P_lm		10

;#define CYCLE_JR_e		12
;#define CYCLE_JR_Z_e		7
;#define CYCLE_JR_NZ_e		7
;#define CYCLE_JR_C_e		7
;#define CYCLE_JR_NC_e		7

;#define CYCLE_DJNZ_e		8

;****************************************************************************
;	Call and Return Group
;****************************************************************************

;#define CYCLE_CALL_lm		17
;#define CYCLE_CALL_Z_lm		10
;#define CYCLE_CALL_NZ_lm	10
;#define CYCLE_CALL_C_lm		10
;#define CYCLE_CALL_NC_lm	10
;#define CYCLE_CALL_PE_lm	10
;#define CYCLE_CALL_PO_lm	10
;#define CYCLE_CALL_M_lm		10
;#define CYCLE_CALL_P_lm		10

;#define CYCLE_RET		10
;#define CYCLE_RET_Z		5
;#define CYCLE_RET_NZ		5
;#define CYCLE_RET_C		5
;#define CYCLE_RET_NC		5
;#define CYCLE_RET_PE		5
;#define CYCLE_RET_PO		5
;#define CYCLE_RET_M		5
;#define CYCLE_RET_P		5

;#define CYCLE_RETI		14
;#define CYCLE_RETN		14

;#define CYCLE_RST_00H		11
;#define CYCLE_RST_08H		11
;#define CYCLE_RST_10H		11
;#define CYCLE_RST_18H		11
;#define CYCLE_RST_20H		11
;#define CYCLE_RST_28H		11
;#define CYCLE_RST_30H		11
;#define CYCLE_RST_38H		11

;****************************************************************************
;	Input and Output Group
;****************************************************************************

;#define CYCLE_IN_A_ICI		12
;#define CYCLE_IN_B_ICI		12
;#define CYCLE_IN_C_ICI		12
;#define CYCLE_IN_D_ICI		12
;#define CYCLE_IN_E_ICI		12
;#define CYCLE_IN_H_ICI		12
;#define CYCLE_IN_L_ICI		12
;#define CYCLE_IN_A_InI		11

;#define CYCLE_INI		16
;#define CYCLE_INIR		16
;#define CYCLE_IND		16
;#define CYCLE_INDR		16

;#define CYCLE_OUT_ICI_A		12
;#define CYCLE_OUT_ICI_B		12
;#define CYCLE_OUT_ICI_C		12
;#define CYCLE_OUT_ICI_D		12
;#define CYCLE_OUT_ICI_E		12
;#define CYCLE_OUT_ICI_H		12
;#define CYCLE_OUT_ICI_L		12
;#define CYCLE_OUT_InI_A		11

;#define CYCLE_OUTI		16
;#define CYCLE_OTIR		16
;#define CYCLE_OUTD		16
;#define CYCLE_OTDR		16

;****************************************************************************
;	
;****************************************************************************

;****************************************************************************
;	
;****************************************************************************

	.code
	.align 0

;
;	* Z80フラグレジスタ形式から、S1C33 %psrレジスタ形式への変換テーブルです。
;
;	- Z80形式のうち、非公開仕様であるXとYは%psr形式へ変換されません。
;	  X(bit3)およびY(bit5)が0でも1でも、変換結果のC33形式は同じ値になります。
;	  従って、変換前にXとYを0にマスクする必要はありません。
;
;	- C33形式は、C(bit3)、P(bit2)、Z(bit1)、S(bit0)のみを利用します。
;	  C33仕様では符号フラグ(bit0)を"N"と呼びますが、Z80形式と一致させるために、
;	  本モジュールのコメントでは"S"に統一してあります。
;	  以上の4bitに加えて、N(bit5)、H(bit4)を追加しました。
;	  Z80形式の同名ビット(加減算フラグ、ハーフキャリーフラグ)に対応します。
;	  (本当の%psrのbit5-4は、0固定ビットとIEですが、これらは利用しません。)
;
;	- プログラム中で、Nフラグをセットするために、orではなくaddを使っています。
;	  <例>	xoor %F, %F, NF
;		  ではなく
;		xand %F, %F, NF
;	  NF=32なので、or sign6では2命令になってしまいますが、add imm6ならば1命令で済むからです。
;	  NFフラグをセットする前にNFフラグが確実にリセットされている場合は、addを使ってください。
;	  既にNFフラグがセットされている可能性がある場合は、addでは誤った結果になってしまうので、
;	  orを使ってください。
;	  以上の内容は、NFフラグ単独だけではなく、NFを含む複数フラグのセットの場合も同じです。
;	  <例>	xoor %F, %F, NF|HF
;		  ではなく
;		xand %F, %F, NF|HF
;
;	// [テーブルを生成するプログラム]
;	// Z80 Flag-XY    C33 %psr+HC
;	// ----------- => -----------
;	// F(SZ-H-PNC)    F(00NHCPZS)
;	for(i = 0; i < 256; i++) {
;		printf("0x%02x,",
;			((i >> 7) & 1) << 0 | /* S */
;			((i >> 6) & 1) << 1 | /* Z */
;			((i >> 2) & 1) << 2 | /* P */
;			((i >> 0) & 1) << 3 | /* C */
;			((i >> 4) & 1) << 4 | /* H */
;			((i >> 1) & 1) << 5); /* N */
;	}
;
	.global z80cpu_f2psr
z80cpu_f2psr:
	.byte 0x00,0x08,0x20,0x28,0x04,0x0c,0x24,0x2c,0x00,0x08,0x20,0x28,0x04,0x0c,0x24,0x2c
	.byte 0x10,0x18,0x30,0x38,0x14,0x1c,0x34,0x3c,0x10,0x18,0x30,0x38,0x14,0x1c,0x34,0x3c
	.byte 0x00,0x08,0x20,0x28,0x04,0x0c,0x24,0x2c,0x00,0x08,0x20,0x28,0x04,0x0c,0x24,0x2c
	.byte 0x10,0x18,0x30,0x38,0x14,0x1c,0x34,0x3c,0x10,0x18,0x30,0x38,0x14,0x1c,0x34,0x3c
	.byte 0x02,0x0a,0x22,0x2a,0x06,0x0e,0x26,0x2e,0x02,0x0a,0x22,0x2a,0x06,0x0e,0x26,0x2e
	.byte 0x12,0x1a,0x32,0x3a,0x16,0x1e,0x36,0x3e,0x12,0x1a,0x32,0x3a,0x16,0x1e,0x36,0x3e
	.byte 0x02,0x0a,0x22,0x2a,0x06,0x0e,0x26,0x2e,0x02,0x0a,0x22,0x2a,0x06,0x0e,0x26,0x2e
	.byte 0x12,0x1a,0x32,0x3a,0x16,0x1e,0x36,0x3e,0x12,0x1a,0x32,0x3a,0x16,0x1e,0x36,0x3e
	.byte 0x01,0x09,0x21,0x29,0x05,0x0d,0x25,0x2d,0x01,0x09,0x21,0x29,0x05,0x0d,0x25,0x2d
	.byte 0x11,0x19,0x31,0x39,0x15,0x1d,0x35,0x3d,0x11,0x19,0x31,0x39,0x15,0x1d,0x35,0x3d
	.byte 0x01,0x09,0x21,0x29,0x05,0x0d,0x25,0x2d,0x01,0x09,0x21,0x29,0x05,0x0d,0x25,0x2d
	.byte 0x11,0x19,0x31,0x39,0x15,0x1d,0x35,0x3d,0x11,0x19,0x31,0x39,0x15,0x1d,0x35,0x3d
	.byte 0x03,0x0b,0x23,0x2b,0x07,0x0f,0x27,0x2f,0x03,0x0b,0x23,0x2b,0x07,0x0f,0x27,0x2f
	.byte 0x13,0x1b,0x33,0x3b,0x17,0x1f,0x37,0x3f,0x13,0x1b,0x33,0x3b,0x17,0x1f,0x37,0x3f
	.byte 0x03,0x0b,0x23,0x2b,0x07,0x0f,0x27,0x2f,0x03,0x0b,0x23,0x2b,0x07,0x0f,0x27,0x2f
	.byte 0x13,0x1b,0x33,0x3b,0x17,0x1f,0x37,0x3f,0x13,0x1b,0x33,0x3b,0x17,0x1f,0x37,0x3f

;
;	* S1C33 %psrレジスタ形式から、Z80フラグレジスタ形式への変換テーブルです。
;
;	- z80cpu_f2psrのコメントを参照してください。
;
;	- 本モジュールの仕様では、C33形式のbit7-6は0固定でなければいけません。
;	  z80cpu_psr2fのテーブルエントリ数は64しかありません。(bit7-6="00"に依存)
;	  bit7-6のいずれか若しくは両方が1の場合、不正な変換結果になるので注意してください。
;
;	// [テーブルを生成するプログラム]
;	// C33 %psr+HC    Z80 Flag-XY
;	// ----------- => -----------
;	// F(00NHCPZS)    F(SZ-H-PNC)
;	for(i = 0; i < 64; i++) {
;		printf("0x%02x,",
;			((i >> 0) & 1) << 7 | /* S */
;			((i >> 1) & 1) << 6 | /* Z */
;			((i >> 2) & 1) << 2 | /* P */
;			((i >> 3) & 1) << 0 | /* C */
;			((i >> 4) & 1) << 4 | /* H */
;			((i >> 5) & 1) << 1); /* N */
;	}
;
	.global z80cpu_psr2f
z80cpu_psr2f:
	.byte 0x00,0x80,0x40,0xc0,0x04,0x84,0x44,0xc4,0x01,0x81,0x41,0xc1,0x05,0x85,0x45,0xc5
	.byte 0x10,0x90,0x50,0xd0,0x14,0x94,0x54,0xd4,0x11,0x91,0x51,0xd1,0x15,0x95,0x55,0xd5
	.byte 0x02,0x82,0x42,0xc2,0x06,0x86,0x46,0xc6,0x03,0x83,0x43,0xc3,0x07,0x87,0x47,0xc7
	.byte 0x12,0x92,0x52,0xd2,0x16,0x96,0x56,0xd6,0x13,0x93,0x53,0xd3,0x17,0x97,0x57,0xd7

;
;	* 0〜255の1バイト値に対応する、偶数パリティフラグビットの変換表です。
;
;	- パリティフラグビットはZ80形式でもC33形式でも同じ位置(bit2)にありますので、
;	  どちらの用途にも利用可能です。
;	  実際のプログラムでは、C33形式へのマージとして利用しています。
;
	.global z80cpu_parity
z80cpu_parity:
	.byte 4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0
	.byte 0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4
	.byte 0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4
	.byte 4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0
	.byte 0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4
	.byte 4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0
	.byte 4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0
	.byte 0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4

;----------------------------------------------------------------------------

	.code
	.align 2

	.global z80cpu_XXops
z80cpu_XXops:
	.word z80cpu_NOP		;00
	.word z80cpu_LD_BC_lm		;01
	.word z80cpu_LD_IBCI_A		;02
	.word z80cpu_INC_BC		;03
	.word z80cpu_INC_B		;04
	.word z80cpu_DEC_B		;05
	.word z80cpu_LD_B_n		;06
	.word z80cpu_RLCA		;07
	.word z80cpu_EX_AF_AF2		;08
	.word z80cpu_ADD_HL_BC		;09
	.word z80cpu_LD_A_IBCI		;0A
	.word z80cpu_DEC_BC		;0B
	.word z80cpu_INC_C		;0C
	.word z80cpu_DEC_C		;0D
	.word z80cpu_LD_C_n		;0E
	.word z80cpu_RRCA		;0F
	.word z80cpu_DJNZ_e		;10
	.word z80cpu_LD_DE_lm		;11
	.word z80cpu_LD_IDEI_A		;12
	.word z80cpu_INC_DE		;13
	.word z80cpu_INC_D		;14
	.word z80cpu_DEC_D		;15
	.word z80cpu_LD_D_n		;16
	.word z80cpu_RLA		;17
	.word z80cpu_JR_e		;18
	.word z80cpu_ADD_HL_DE		;19
	.word z80cpu_LD_A_IDEI		;1A
	.word z80cpu_DEC_DE		;1B
	.word z80cpu_INC_E		;1C
	.word z80cpu_DEC_E		;1D
	.word z80cpu_LD_E_n		;1E
	.word z80cpu_RRA		;1F
	.word z80cpu_JR_NZ_e		;20
	.word z80cpu_LD_HL_lm		;21
	.word z80cpu_LD_IlmI_HL		;22
	.word z80cpu_INC_HL		;23
	.word z80cpu_INC_H		;24
	.word z80cpu_DEC_H		;25
	.word z80cpu_LD_H_n		;26
	.word z80cpu_DAA		;27
	.word z80cpu_JR_Z_e		;28
	.word z80cpu_ADD_HL_HL		;29
	.word z80cpu_LD_HL_IlmI		;2A
	.word z80cpu_DEC_HL		;2B
	.word z80cpu_INC_L		;2C
	.word z80cpu_DEC_L		;2D
	.word z80cpu_LD_L_n		;2E
	.word z80cpu_CPL		;2F
	.word z80cpu_JR_NC_e		;30
	.word z80cpu_LD_SP_lm		;31
	.word z80cpu_LD_IlmI_A		;32
	.word z80cpu_INC_SP		;33
	.word z80cpu_INC_IHLI		;34
	.word z80cpu_DEC_IHLI		;35
	.word z80cpu_LD_IHLI_n		;36
	.word z80cpu_SCF		;37
	.word z80cpu_JR_C_e		;38
	.word z80cpu_ADD_HL_SP		;39
	.word z80cpu_LD_A_IlmI		;3A
	.word z80cpu_DEC_SP		;3B
	.word z80cpu_INC_A		;3C
	.word z80cpu_DEC_A		;3D
	.word z80cpu_LD_A_n		;3E
	.word z80cpu_CCF		;3F
	.word z80cpu_LD_B_B		;40
	.word z80cpu_LD_B_C		;41
	.word z80cpu_LD_B_D		;42
	.word z80cpu_LD_B_E		;43
	.word z80cpu_LD_B_H		;44
	.word z80cpu_LD_B_L		;45
	.word z80cpu_LD_B_IHLI		;46
	.word z80cpu_LD_B_A		;47
	.word z80cpu_LD_C_B		;48
	.word z80cpu_LD_C_C		;49
	.word z80cpu_LD_C_D		;4A
	.word z80cpu_LD_C_E		;4B
	.word z80cpu_LD_C_H		;4C
	.word z80cpu_LD_C_L		;4D
	.word z80cpu_LD_C_IHLI		;4E
	.word z80cpu_LD_C_A		;4F
	.word z80cpu_LD_D_B		;50
	.word z80cpu_LD_D_C		;51
	.word z80cpu_LD_D_D		;52
	.word z80cpu_LD_D_E		;53
	.word z80cpu_LD_D_H		;54
	.word z80cpu_LD_D_L		;55
	.word z80cpu_LD_D_IHLI		;56
	.word z80cpu_LD_D_A		;57
	.word z80cpu_LD_E_B		;58
	.word z80cpu_LD_E_C		;59
	.word z80cpu_LD_E_D		;5A
	.word z80cpu_LD_E_E		;5B
	.word z80cpu_LD_E_H		;5C
	.word z80cpu_LD_E_L		;5D
	.word z80cpu_LD_E_IHLI		;5E
	.word z80cpu_LD_E_A		;5F
	.word z80cpu_LD_H_B		;60
	.word z80cpu_LD_H_C		;61
	.word z80cpu_LD_H_D		;62
	.word z80cpu_LD_H_E		;63
	.word z80cpu_LD_H_H		;64
	.word z80cpu_LD_H_L		;65
	.word z80cpu_LD_H_IHLI		;66
	.word z80cpu_LD_H_A		;67
	.word z80cpu_LD_L_B		;68
	.word z80cpu_LD_L_C		;69
	.word z80cpu_LD_L_D		;6A
	.word z80cpu_LD_L_E		;6B
	.word z80cpu_LD_L_H		;6C
	.word z80cpu_LD_L_L		;6D
	.word z80cpu_LD_L_IHLI		;6E
	.word z80cpu_LD_L_A		;6F
	.word z80cpu_LD_IHLI_B		;70
	.word z80cpu_LD_IHLI_C		;71
	.word z80cpu_LD_IHLI_D		;72
	.word z80cpu_LD_IHLI_E		;73
	.word z80cpu_LD_IHLI_H		;74
	.word z80cpu_LD_IHLI_L		;75
	.word z80cpu_HALT		;76
	.word z80cpu_LD_IHLI_A		;77
	.word z80cpu_LD_A_B		;78
	.word z80cpu_LD_A_C		;79
	.word z80cpu_LD_A_D		;7A
	.word z80cpu_LD_A_E		;7B
	.word z80cpu_LD_A_H		;7C
	.word z80cpu_LD_A_L		;7D
	.word z80cpu_LD_A_IHLI		;7E
	.word z80cpu_LD_A_A		;7F
	.word z80cpu_ADD_A_B		;80
	.word z80cpu_ADD_A_C		;81
	.word z80cpu_ADD_A_D		;82
	.word z80cpu_ADD_A_E		;83
	.word z80cpu_ADD_A_H		;84
	.word z80cpu_ADD_A_L		;85
	.word z80cpu_ADD_A_IHLI		;86
	.word z80cpu_ADD_A_A		;87
	.word z80cpu_ADC_A_B		;88
	.word z80cpu_ADC_A_C		;89
	.word z80cpu_ADC_A_D		;8A
	.word z80cpu_ADC_A_E		;8B
	.word z80cpu_ADC_A_H		;8C
	.word z80cpu_ADC_A_L		;8D
	.word z80cpu_ADC_A_IHLI		;8E
	.word z80cpu_ADC_A_A		;8F
	.word z80cpu_SUB_B		;90
	.word z80cpu_SUB_C		;91
	.word z80cpu_SUB_D		;92
	.word z80cpu_SUB_E		;93
	.word z80cpu_SUB_H		;94
	.word z80cpu_SUB_L		;95
	.word z80cpu_SUB_IHLI		;96
	.word z80cpu_SUB_A		;97
	.word z80cpu_SBC_A_B		;98
	.word z80cpu_SBC_A_C		;99
	.word z80cpu_SBC_A_D		;9A
	.word z80cpu_SBC_A_E		;9B
	.word z80cpu_SBC_A_H		;9C
	.word z80cpu_SBC_A_L		;9D
	.word z80cpu_SBC_A_IHLI		;9E
	.word z80cpu_SBC_A_A		;9F
	.word z80cpu_AND_B		;A0
	.word z80cpu_AND_C		;A1
	.word z80cpu_AND_D		;A2
	.word z80cpu_AND_E		;A3
	.word z80cpu_AND_H		;A4
	.word z80cpu_AND_L		;A5
	.word z80cpu_AND_IHLI		;A6
	.word z80cpu_AND_A		;A7
	.word z80cpu_XOR_B		;A8
	.word z80cpu_XOR_C		;A9
	.word z80cpu_XOR_D		;AA
	.word z80cpu_XOR_E		;AB
	.word z80cpu_XOR_H		;AC
	.word z80cpu_XOR_L		;AD
	.word z80cpu_XOR_IHLI		;AE
	.word z80cpu_XOR_A		;AF
	.word z80cpu_OR_B		;B0
	.word z80cpu_OR_C		;B1
	.word z80cpu_OR_D		;B2
	.word z80cpu_OR_E		;B3
	.word z80cpu_OR_H		;B4
	.word z80cpu_OR_L		;B5
	.word z80cpu_OR_IHLI		;B6
	.word z80cpu_OR_A		;B7
	.word z80cpu_CP_B		;B8
	.word z80cpu_CP_C		;B9
	.word z80cpu_CP_D		;BA
	.word z80cpu_CP_E		;BB
	.word z80cpu_CP_H		;BC
	.word z80cpu_CP_L		;BD
	.word z80cpu_CP_IHLI		;BE
	.word z80cpu_CP_A		;BF
	.word z80cpu_RET_NZ		;C0
	.word z80cpu_POP_BC		;C1
	.word z80cpu_JP_NZ_lm		;C2
	.word z80cpu_JP_lm		;C3
	.word z80cpu_CALL_NZ_lm		;C4
	.word z80cpu_PUSH_BC		;C5
	.word z80cpu_ADD_A_n		;C6
	.word z80cpu_RST_00H		;C7
	.word z80cpu_RET_Z		;C8
	.word z80cpu_RET		;C9
	.word z80cpu_JP_Z_lm		;CA
	.word z80cpu_CB			;CB
	.word z80cpu_CALL_Z_lm		;CC
	.word z80cpu_CALL_lm		;CD
	.word z80cpu_ADC_A_n		;CE
	.word z80cpu_RST_08H		;CF
	.word z80cpu_RET_NC		;D0
	.word z80cpu_POP_DE		;D1
	.word z80cpu_JP_NC_lm		;D2
	.word z80cpu_OUT_InI_A		;D3
	.word z80cpu_CALL_NC_lm		;D4
	.word z80cpu_PUSH_DE		;D5
	.word z80cpu_SUB_n		;D6
	.word z80cpu_RST_10H		;D7
	.word z80cpu_RET_C		;D8
	.word z80cpu_EXX		;D9
	.word z80cpu_JP_C_lm		;DA
	.word z80cpu_IN_A_InI		;DB
	.word z80cpu_CALL_C_lm		;DC
	.word z80cpu_DD			;DD
	.word z80cpu_SBC_A_n		;DE
	.word z80cpu_RST_18H		;DF
	.word z80cpu_RET_PO		;E0
	.word z80cpu_POP_HL		;E1
	.word z80cpu_JP_PO_lm		;E2
	.word z80cpu_EX_ISPI_HL		;E3
	.word z80cpu_CALL_PO_lm		;E4
	.word z80cpu_PUSH_HL		;E5
	.word z80cpu_AND_n		;E6
	.word z80cpu_RST_20H		;E7
	.word z80cpu_RET_PE		;E8
	.word z80cpu_JP_IHLI		;E9
	.word z80cpu_JP_PE_lm		;EA
	.word z80cpu_EX_DE_HL		;EB
	.word z80cpu_CALL_PE_lm		;EC
	.word z80cpu_ED			;ED
	.word z80cpu_XOR_n		;EE
	.word z80cpu_RST_28H		;EF
	.word z80cpu_RET_P		;F0
	.word z80cpu_POP_AF		;F1
	.word z80cpu_JP_P_lm		;F2
	.word z80cpu_DI			;F3
	.word z80cpu_CALL_P_lm		;F4
	.word z80cpu_PUSH_AF		;F5
	.word z80cpu_OR_n		;F6
	.word z80cpu_RST_30H		;F7
	.word z80cpu_RET_M		;F8
	.word z80cpu_LD_SP_HL		;F9
	.word z80cpu_JP_M_lm		;FA
	.word z80cpu_EI			;FB
	.word z80cpu_CALL_M_lm		;FC
	.word z80cpu_FD			;FD
	.word z80cpu_CP_n		;FE
	.word z80cpu_RST_38H		;FF

	.global z80cpu_CBops
z80cpu_CBops:
	.word z80cpu_RLC_B		;00
	.word z80cpu_RLC_C		;01
	.word z80cpu_RLC_D		;02
	.word z80cpu_RLC_E		;03
	.word z80cpu_RLC_H		;04
	.word z80cpu_RLC_L		;05
	.word z80cpu_RLC_IHLI		;06
	.word z80cpu_RLC_A		;07
	.word z80cpu_RRC_B		;08
	.word z80cpu_RRC_C		;09
	.word z80cpu_RRC_D		;0A
	.word z80cpu_RRC_E		;0B
	.word z80cpu_RRC_H		;0C
	.word z80cpu_RRC_L		;0D
	.word z80cpu_RRC_IHLI		;0E
	.word z80cpu_RRC_A		;0F
	.word z80cpu_RL_B		;10
	.word z80cpu_RL_C		;11
	.word z80cpu_RL_D		;12
	.word z80cpu_RL_E		;13
	.word z80cpu_RL_H		;14
	.word z80cpu_RL_L		;15
	.word z80cpu_RL_IHLI		;16
	.word z80cpu_RL_A		;17
	.word z80cpu_RR_B		;18
	.word z80cpu_RR_C		;19
	.word z80cpu_RR_D		;1A
	.word z80cpu_RR_E		;1B
	.word z80cpu_RR_H		;1C
	.word z80cpu_RR_L		;1D
	.word z80cpu_RR_IHLI		;1E
	.word z80cpu_RR_A		;1F
	.word z80cpu_SLA_B		;20
	.word z80cpu_SLA_C		;21
	.word z80cpu_SLA_D		;22
	.word z80cpu_SLA_E		;23
	.word z80cpu_SLA_H		;24
	.word z80cpu_SLA_L		;25
	.word z80cpu_SLA_IHLI		;26
	.word z80cpu_SLA_A		;27
	.word z80cpu_SRA_B		;28
	.word z80cpu_SRA_C		;29
	.word z80cpu_SRA_D		;2A
	.word z80cpu_SRA_E		;2B
	.word z80cpu_SRA_H		;2C
	.word z80cpu_SRA_L		;2D
	.word z80cpu_SRA_IHLI		;2E
	.word z80cpu_SRA_A		;2F
	.word z80cpu_ERROR		;30
	.word z80cpu_ERROR		;31
	.word z80cpu_ERROR		;32
	.word z80cpu_ERROR		;33
	.word z80cpu_ERROR		;34
	.word z80cpu_ERROR		;35
	.word z80cpu_ERROR		;36
	.word z80cpu_ERROR		;37
	.word z80cpu_SRL_B		;38
	.word z80cpu_SRL_C		;39
	.word z80cpu_SRL_D		;3A
	.word z80cpu_SRL_E		;3B
	.word z80cpu_SRL_H		;3C
	.word z80cpu_SRL_L		;3D
	.word z80cpu_SRL_IHLI		;3E
	.word z80cpu_SRL_A		;3F
	.word z80cpu_BIT_0_B		;40
	.word z80cpu_BIT_0_C		;41
	.word z80cpu_BIT_0_D		;42
	.word z80cpu_BIT_0_E		;43
	.word z80cpu_BIT_0_H		;44
	.word z80cpu_BIT_0_L		;45
	.word z80cpu_BIT_0_IHLI		;46
	.word z80cpu_BIT_0_A		;47
	.word z80cpu_BIT_1_B		;48
	.word z80cpu_BIT_1_C		;49
	.word z80cpu_BIT_1_D		;4A
	.word z80cpu_BIT_1_E		;4B
	.word z80cpu_BIT_1_H		;4C
	.word z80cpu_BIT_1_L		;4D
	.word z80cpu_BIT_1_IHLI		;4E
	.word z80cpu_BIT_1_A		;4F
	.word z80cpu_BIT_2_B		;50
	.word z80cpu_BIT_2_C		;51
	.word z80cpu_BIT_2_D		;52
	.word z80cpu_BIT_2_E		;53
	.word z80cpu_BIT_2_H		;54
	.word z80cpu_BIT_2_L		;55
	.word z80cpu_BIT_2_IHLI		;56
	.word z80cpu_BIT_2_A		;57
	.word z80cpu_BIT_3_B		;58
	.word z80cpu_BIT_3_C		;59
	.word z80cpu_BIT_3_D		;5A
	.word z80cpu_BIT_3_E		;5B
	.word z80cpu_BIT_3_H		;5C
	.word z80cpu_BIT_3_L		;5D
	.word z80cpu_BIT_3_IHLI		;5E
	.word z80cpu_BIT_3_A		;5F
	.word z80cpu_BIT_4_B		;60
	.word z80cpu_BIT_4_C		;61
	.word z80cpu_BIT_4_D		;62
	.word z80cpu_BIT_4_E		;63
	.word z80cpu_BIT_4_H		;64
	.word z80cpu_BIT_4_L		;65
	.word z80cpu_BIT_4_IHLI		;66
	.word z80cpu_BIT_4_A		;67
	.word z80cpu_BIT_5_B		;68
	.word z80cpu_BIT_5_C		;69
	.word z80cpu_BIT_5_D		;6A
	.word z80cpu_BIT_5_E		;6B
	.word z80cpu_BIT_5_H		;6C
	.word z80cpu_BIT_5_L		;6D
	.word z80cpu_BIT_5_IHLI		;6E
	.word z80cpu_BIT_5_A		;6F
	.word z80cpu_BIT_6_B		;70
	.word z80cpu_BIT_6_C		;71
	.word z80cpu_BIT_6_D		;72
	.word z80cpu_BIT_6_E		;73
	.word z80cpu_BIT_6_H		;74
	.word z80cpu_BIT_6_L		;75
	.word z80cpu_BIT_6_IHLI		;76
	.word z80cpu_BIT_6_A		;77
	.word z80cpu_BIT_7_B		;78
	.word z80cpu_BIT_7_C		;79
	.word z80cpu_BIT_7_D		;7A
	.word z80cpu_BIT_7_E		;7B
	.word z80cpu_BIT_7_H		;7C
	.word z80cpu_BIT_7_L		;7D
	.word z80cpu_BIT_7_IHLI		;7E
	.word z80cpu_BIT_7_A		;7F
	.word z80cpu_RES_0_B		;80
	.word z80cpu_RES_0_C		;81
	.word z80cpu_RES_0_D		;82
	.word z80cpu_RES_0_E		;83
	.word z80cpu_RES_0_H		;84
	.word z80cpu_RES_0_L		;85
	.word z80cpu_RES_0_IHLI		;86
	.word z80cpu_RES_0_A		;87
	.word z80cpu_RES_1_B		;88
	.word z80cpu_RES_1_C		;89
	.word z80cpu_RES_1_D		;8A
	.word z80cpu_RES_1_E		;8B
	.word z80cpu_RES_1_H		;8C
	.word z80cpu_RES_1_L		;8D
	.word z80cpu_RES_1_IHLI		;8E
	.word z80cpu_RES_1_A		;8F
	.word z80cpu_RES_2_B		;90
	.word z80cpu_RES_2_C		;91
	.word z80cpu_RES_2_D		;92
	.word z80cpu_RES_2_E		;93
	.word z80cpu_RES_2_H		;94
	.word z80cpu_RES_2_L		;95
	.word z80cpu_RES_2_IHLI		;96
	.word z80cpu_RES_2_A		;97
	.word z80cpu_RES_3_B		;98
	.word z80cpu_RES_3_C		;99
	.word z80cpu_RES_3_D		;9A
	.word z80cpu_RES_3_E		;9B
	.word z80cpu_RES_3_H		;9C
	.word z80cpu_RES_3_L		;9D
	.word z80cpu_RES_3_IHLI		;9E
	.word z80cpu_RES_3_A		;9F
	.word z80cpu_RES_4_B		;A0
	.word z80cpu_RES_4_C		;A1
	.word z80cpu_RES_4_D		;A2
	.word z80cpu_RES_4_E		;A3
	.word z80cpu_RES_4_H		;A4
	.word z80cpu_RES_4_L		;A5
	.word z80cpu_RES_4_IHLI		;A6
	.word z80cpu_RES_4_A		;A7
	.word z80cpu_RES_5_B		;A8
	.word z80cpu_RES_5_C		;A9
	.word z80cpu_RES_5_D		;AA
	.word z80cpu_RES_5_E		;AB
	.word z80cpu_RES_5_H		;AC
	.word z80cpu_RES_5_L		;AD
	.word z80cpu_RES_5_IHLI		;AE
	.word z80cpu_RES_5_A		;AF
	.word z80cpu_RES_6_B		;B0
	.word z80cpu_RES_6_C		;B1
	.word z80cpu_RES_6_D		;B2
	.word z80cpu_RES_6_E		;B3
	.word z80cpu_RES_6_H		;B4
	.word z80cpu_RES_6_L		;B5
	.word z80cpu_RES_6_IHLI		;B6
	.word z80cpu_RES_6_A		;B7
	.word z80cpu_RES_7_B		;B8
	.word z80cpu_RES_7_C		;B9
	.word z80cpu_RES_7_D		;BA
	.word z80cpu_RES_7_E		;BB
	.word z80cpu_RES_7_H		;BC
	.word z80cpu_RES_7_L		;BD
	.word z80cpu_RES_7_IHLI		;BE
	.word z80cpu_RES_7_A		;BF
	.word z80cpu_SET_0_B		;C0
	.word z80cpu_SET_0_C		;C1
	.word z80cpu_SET_0_D		;C2
	.word z80cpu_SET_0_E		;C3
	.word z80cpu_SET_0_H		;C4
	.word z80cpu_SET_0_L		;C5
	.word z80cpu_SET_0_IHLI		;C6
	.word z80cpu_SET_0_A		;C7
	.word z80cpu_SET_1_B		;C8
	.word z80cpu_SET_1_C		;C9
	.word z80cpu_SET_1_D		;CA
	.word z80cpu_SET_1_E		;CB
	.word z80cpu_SET_1_H		;CC
	.word z80cpu_SET_1_L		;CD
	.word z80cpu_SET_1_IHLI		;CE
	.word z80cpu_SET_1_A		;CF
	.word z80cpu_SET_2_B		;D0
	.word z80cpu_SET_2_C		;D1
	.word z80cpu_SET_2_D		;D2
	.word z80cpu_SET_2_E		;D3
	.word z80cpu_SET_2_H		;D4
	.word z80cpu_SET_2_L		;D5
	.word z80cpu_SET_2_IHLI		;D6
	.word z80cpu_SET_2_A		;D7
	.word z80cpu_SET_3_B		;D8
	.word z80cpu_SET_3_C		;D9
	.word z80cpu_SET_3_D		;DA
	.word z80cpu_SET_3_E		;DB
	.word z80cpu_SET_3_H		;DC
	.word z80cpu_SET_3_L		;DD
	.word z80cpu_SET_3_IHLI		;DE
	.word z80cpu_SET_3_A		;DF
	.word z80cpu_SET_4_B		;E0
	.word z80cpu_SET_4_C		;E1
	.word z80cpu_SET_4_D		;E2
	.word z80cpu_SET_4_E		;E3
	.word z80cpu_SET_4_H		;E4
	.word z80cpu_SET_4_L		;E5
	.word z80cpu_SET_4_IHLI		;E6
	.word z80cpu_SET_4_A		;E7
	.word z80cpu_SET_5_B		;E8
	.word z80cpu_SET_5_C		;E9
	.word z80cpu_SET_5_D		;EA
	.word z80cpu_SET_5_E		;EB
	.word z80cpu_SET_5_H		;EC
	.word z80cpu_SET_5_L		;ED
	.word z80cpu_SET_5_IHLI		;EE
	.word z80cpu_SET_5_A		;EF
	.word z80cpu_SET_6_B		;F0
	.word z80cpu_SET_6_C		;F1
	.word z80cpu_SET_6_D		;F2
	.word z80cpu_SET_6_E		;F3
	.word z80cpu_SET_6_H		;F4
	.word z80cpu_SET_6_L		;F5
	.word z80cpu_SET_6_IHLI		;F6
	.word z80cpu_SET_6_A		;F7
	.word z80cpu_SET_7_B		;F8
	.word z80cpu_SET_7_C		;F9
	.word z80cpu_SET_7_D		;FA
	.word z80cpu_SET_7_E		;FB
	.word z80cpu_SET_7_H		;FC
	.word z80cpu_SET_7_L		;FD
	.word z80cpu_SET_7_IHLI		;FE
	.word z80cpu_SET_7_A		;FF

	.global z80cpu_EDops
z80cpu_EDops:
	.word z80cpu_ERROR		;00
	.word z80cpu_ERROR		;01
	.word z80cpu_ERROR		;02
	.word z80cpu_ERROR		;03
	.word z80cpu_ERROR		;04
	.word z80cpu_ERROR		;05
	.word z80cpu_ERROR		;06
	.word z80cpu_ERROR		;07
	.word z80cpu_ERROR		;08
	.word z80cpu_ERROR		;09
	.word z80cpu_ERROR		;0A
	.word z80cpu_ERROR		;0B
	.word z80cpu_ERROR		;0C
	.word z80cpu_ERROR		;0D
	.word z80cpu_ERROR		;0E
	.word z80cpu_ERROR		;0F
	.word z80cpu_ERROR		;10
	.word z80cpu_ERROR		;11
	.word z80cpu_ERROR		;12
	.word z80cpu_ERROR		;13
	.word z80cpu_ERROR		;14
	.word z80cpu_ERROR		;15
	.word z80cpu_ERROR		;16
	.word z80cpu_ERROR		;17
	.word z80cpu_ERROR		;18
	.word z80cpu_ERROR		;19
	.word z80cpu_ERROR		;1A
	.word z80cpu_ERROR		;1B
	.word z80cpu_ERROR		;1C
	.word z80cpu_ERROR		;1D
	.word z80cpu_ERROR		;1E
	.word z80cpu_ERROR		;1F
	.word z80cpu_ERROR		;20
	.word z80cpu_ERROR		;21
	.word z80cpu_ERROR		;22
	.word z80cpu_ERROR		;23
	.word z80cpu_ERROR		;24
	.word z80cpu_ERROR		;25
	.word z80cpu_ERROR		;26
	.word z80cpu_ERROR		;27
	.word z80cpu_ERROR		;28
	.word z80cpu_ERROR		;29
	.word z80cpu_ERROR		;2A
	.word z80cpu_ERROR		;2B
	.word z80cpu_ERROR		;2C
	.word z80cpu_ERROR		;2D
	.word z80cpu_ERROR		;2E
	.word z80cpu_ERROR		;2F
	.word z80cpu_ERROR		;30
	.word z80cpu_ERROR		;31
	.word z80cpu_ERROR		;32
	.word z80cpu_ERROR		;33
	.word z80cpu_ERROR		;34
	.word z80cpu_ERROR		;35
	.word z80cpu_ERROR		;36
	.word z80cpu_ERROR		;37
	.word z80cpu_ERROR		;38
	.word z80cpu_ERROR		;39
	.word z80cpu_ERROR		;3A
	.word z80cpu_ERROR		;3B
	.word z80cpu_ERROR		;3C
	.word z80cpu_ERROR		;3D
	.word z80cpu_ERROR		;3E
	.word z80cpu_ERROR		;3F
	.word z80cpu_IN_B_ICI		;40
	.word z80cpu_OUT_ICI_B		;41
	.word z80cpu_SBC_HL_BC		;42
	.word z80cpu_LD_IlmI_BC		;43
	.word z80cpu_NEG		;44
	.word z80cpu_RETN		;45
	.word z80cpu_IM_0		;46
	.word z80cpu_LD_I_A		;47
	.word z80cpu_IN_C_ICI		;48
	.word z80cpu_OUT_ICI_C		;49
	.word z80cpu_ADC_HL_BC		;4A
	.word z80cpu_LD_BC_IlmI		;4B
	.word z80cpu_ERROR		;4C
	.word z80cpu_RETI		;4D
	.word z80cpu_ERROR		;4E
	.word z80cpu_LD_R_A		;4F
	.word z80cpu_IN_D_ICI		;50
	.word z80cpu_OUT_ICI_D		;51
	.word z80cpu_SBC_HL_DE		;52
	.word z80cpu_LD_IlmI_DE		;53
	.word z80cpu_ERROR		;54
	.word z80cpu_ERROR		;55
	.word z80cpu_IM_1		;56
	.word z80cpu_LD_A_I		;57
	.word z80cpu_IN_E_ICI		;58
	.word z80cpu_OUT_ICI_E		;59
	.word z80cpu_ADC_HL_DE		;5A
	.word z80cpu_LD_DE_IlmI		;5B
	.word z80cpu_ERROR		;5C
	.word z80cpu_ERROR		;5D
	.word z80cpu_IM_2		;5E
	.word z80cpu_LD_A_R		;5F
	.word z80cpu_IN_H_ICI		;60
	.word z80cpu_OUT_ICI_H		;61
	.word z80cpu_SBC_HL_HL		;62
	.word z80cpu_ERROR		;63
	.word z80cpu_ERROR		;64
	.word z80cpu_ERROR		;65
	.word z80cpu_ERROR		;66
	.word z80cpu_RRD		;67
	.word z80cpu_IN_L_ICI		;68
	.word z80cpu_OUT_ICI_L		;69
	.word z80cpu_ADC_HL_HL		;6A
	.word z80cpu_ERROR		;6B
	.word z80cpu_ERROR		;6C
	.word z80cpu_ERROR		;6D
	.word z80cpu_ERROR		;6E
	.word z80cpu_RLD		;6F
	.word z80cpu_ERROR		;70
	.word z80cpu_ERROR		;71
	.word z80cpu_SBC_HL_SP		;72
	.word z80cpu_LD_IlmI_SP		;73
	.word z80cpu_ERROR		;74
	.word z80cpu_ERROR		;75
	.word z80cpu_ERROR		;76
	.word z80cpu_ERROR		;77
	.word z80cpu_IN_A_ICI		;78
	.word z80cpu_OUT_ICI_A		;79
	.word z80cpu_ADC_HL_SP		;7A
	.word z80cpu_LD_SP_IlmI		;7B
	.word z80cpu_ERROR		;7C
	.word z80cpu_ERROR		;7D
	.word z80cpu_ERROR		;7E
	.word z80cpu_ERROR		;7F
	.word z80cpu_ERROR		;80
	.word z80cpu_ERROR		;81
	.word z80cpu_ERROR		;82
	.word z80cpu_ERROR		;83
	.word z80cpu_ERROR		;84
	.word z80cpu_ERROR		;85
	.word z80cpu_ERROR		;86
	.word z80cpu_ERROR		;87
	.word z80cpu_ERROR		;88
	.word z80cpu_ERROR		;89
	.word z80cpu_ERROR		;8A
	.word z80cpu_ERROR		;8B
	.word z80cpu_ERROR		;8C
	.word z80cpu_ERROR		;8D
	.word z80cpu_ERROR		;8E
	.word z80cpu_ERROR		;8F
	.word z80cpu_ERROR		;90
	.word z80cpu_ERROR		;91
	.word z80cpu_ERROR		;92
	.word z80cpu_ERROR		;93
	.word z80cpu_ERROR		;94
	.word z80cpu_ERROR		;95
	.word z80cpu_ERROR		;96
	.word z80cpu_ERROR		;97
	.word z80cpu_ERROR		;98
	.word z80cpu_ERROR		;99
	.word z80cpu_ERROR		;9A
	.word z80cpu_ERROR		;9B
	.word z80cpu_ERROR		;9C
	.word z80cpu_ERROR		;9D
	.word z80cpu_ERROR		;9E
	.word z80cpu_ERROR		;9F
	.word z80cpu_LDI		;A0
	.word z80cpu_CPI		;A1
	.word z80cpu_INI		;A2
	.word z80cpu_OUTI		;A3
	.word z80cpu_ERROR		;A4
	.word z80cpu_ERROR		;A5
	.word z80cpu_ERROR		;A6
	.word z80cpu_ERROR		;A7
	.word z80cpu_LDD		;A8
	.word z80cpu_CPD		;A9
	.word z80cpu_IND		;AA
	.word z80cpu_OUTD		;AB
	.word z80cpu_ERROR		;AC
	.word z80cpu_ERROR		;AD
	.word z80cpu_ERROR		;AE
	.word z80cpu_ERROR		;AF
	.word z80cpu_LDIR		;B0
	.word z80cpu_CPIR		;B1
	.word z80cpu_INIR		;B2
	.word z80cpu_OTIR		;B3
	.word z80cpu_ERROR		;B4
	.word z80cpu_ERROR		;B5
	.word z80cpu_ERROR		;B6
	.word z80cpu_ERROR		;B7
	.word z80cpu_LDDR		;B8
	.word z80cpu_CPDR		;B9
	.word z80cpu_INDR		;BA
	.word z80cpu_OTDR		;BB
	.word z80cpu_ERROR		;BC
	.word z80cpu_ERROR		;BD
	.word z80cpu_ERROR		;BE
	.word z80cpu_ERROR		;BF
	.word z80cpu_ERROR		;C0
	.word z80cpu_ERROR		;C1
	.word z80cpu_ERROR		;C2
	.word z80cpu_ERROR		;C3
	.word z80cpu_ERROR		;C4
	.word z80cpu_ERROR		;C5
	.word z80cpu_ERROR		;C6
	.word z80cpu_ERROR		;C7
	.word z80cpu_ERROR		;C8
	.word z80cpu_ERROR		;C9
	.word z80cpu_ERROR		;CA
	.word z80cpu_ERROR		;CB
	.word z80cpu_ERROR		;CC
	.word z80cpu_ERROR		;CD
	.word z80cpu_ERROR		;CE
	.word z80cpu_ERROR		;CF
	.word z80cpu_ERROR		;D0
	.word z80cpu_ERROR		;D1
	.word z80cpu_ERROR		;D2
	.word z80cpu_ERROR		;D3
	.word z80cpu_ERROR		;D4
	.word z80cpu_ERROR		;D5
	.word z80cpu_ERROR		;D6
	.word z80cpu_ERROR		;D7
	.word z80cpu_ERROR		;D8
	.word z80cpu_ERROR		;D9
	.word z80cpu_ERROR		;DA
	.word z80cpu_ERROR		;DB
	.word z80cpu_ERROR		;DC
	.word z80cpu_ERROR		;DD
	.word z80cpu_ERROR		;DE
	.word z80cpu_ERROR		;DF
	.word z80cpu_ERROR		;E0
	.word z80cpu_ERROR		;E1
	.word z80cpu_ERROR		;E2
	.word z80cpu_ERROR		;E3
	.word z80cpu_ERROR		;E4
	.word z80cpu_ERROR		;E5
	.word z80cpu_ERROR		;E6
	.word z80cpu_ERROR		;E7
	.word z80cpu_ERROR		;E8
	.word z80cpu_ERROR		;E9
	.word z80cpu_ERROR		;EA
	.word z80cpu_ERROR		;EB
	.word z80cpu_ERROR		;EC
	.word z80cpu_ERROR		;ED
	.word z80cpu_ERROR		;EE
	.word z80cpu_ERROR		;EF
	.word z80cpu_ERROR		;F0
	.word z80cpu_ERROR		;F1
	.word z80cpu_ERROR		;F2
	.word z80cpu_ERROR		;F3
	.word z80cpu_ERROR		;F4
	.word z80cpu_ERROR		;F5
	.word z80cpu_ERROR		;F6
	.word z80cpu_ERROR		;F7
	.word z80cpu_ERROR		;F8
	.word z80cpu_ERROR		;F9
	.word z80cpu_ERROR		;FA
	.word z80cpu_ERROR		;FB
	.word z80cpu_ERROR		;FC
	.word z80cpu_ERROR		;FD
	.word z80cpu_ERROR		;FE
	.word z80cpu_ERROR		;FF

	.global z80cpu_DDops
z80cpu_DDops:
	.word z80cpu_ERROR		;00
	.word z80cpu_ERROR		;01
	.word z80cpu_ERROR		;02
	.word z80cpu_ERROR		;03
	.word z80cpu_ERROR		;04
	.word z80cpu_ERROR		;05
	.word z80cpu_ERROR		;06
	.word z80cpu_ERROR		;07
	.word z80cpu_ERROR		;08
	.word z80cpu_ADD_IX_BC		;09
	.word z80cpu_ERROR		;0A
	.word z80cpu_ERROR		;0B
	.word z80cpu_ERROR		;0C
	.word z80cpu_ERROR		;0D
	.word z80cpu_ERROR		;0E
	.word z80cpu_ERROR		;0F
	.word z80cpu_ERROR		;10
	.word z80cpu_ERROR		;11
	.word z80cpu_ERROR		;12
	.word z80cpu_ERROR		;13
	.word z80cpu_ERROR		;14
	.word z80cpu_ERROR		;15
	.word z80cpu_ERROR		;16
	.word z80cpu_ERROR		;17
	.word z80cpu_ERROR		;18
	.word z80cpu_ADD_IX_DE		;19
	.word z80cpu_ERROR		;1A
	.word z80cpu_ERROR		;1B
	.word z80cpu_ERROR		;1C
	.word z80cpu_ERROR		;1D
	.word z80cpu_ERROR		;1E
	.word z80cpu_ERROR		;1F
	.word z80cpu_ERROR		;20
	.word z80cpu_LD_IX_lm		;21
	.word z80cpu_LD_IlmI_IX		;22
	.word z80cpu_INC_IX		;23
	.word z80cpu_INC_IXH		;24
	.word z80cpu_DEC_IXH		;25
	.word z80cpu_LD_IXH_n		;26
	.word z80cpu_ERROR		;27
	.word z80cpu_ERROR		;28
	.word z80cpu_ADD_IX_IX		;29
	.word z80cpu_LD_IX_IlmI		;2A
	.word z80cpu_DEC_IX		;2B
	.word z80cpu_INC_IXL		;2C
	.word z80cpu_DEC_IXL		;2D
	.word z80cpu_LD_IXL_n		;2E
	.word z80cpu_ERROR		;2F
	.word z80cpu_ERROR		;30
	.word z80cpu_ERROR		;31
	.word z80cpu_ERROR		;32
	.word z80cpu_ERROR		;33
	.word z80cpu_INC_IIX_dI		;34
	.word z80cpu_DEC_IIX_dI		;35
	.word z80cpu_LD_IIX_dI_n	;36
	.word z80cpu_ERROR		;37
	.word z80cpu_ERROR		;38
	.word z80cpu_ADD_IX_SP		;39
	.word z80cpu_ERROR		;3A
	.word z80cpu_ERROR		;3B
	.word z80cpu_ERROR		;3C
	.word z80cpu_ERROR		;3D
	.word z80cpu_ERROR		;3E
	.word z80cpu_ERROR		;3F
	.word z80cpu_ERROR		;40
	.word z80cpu_ERROR		;41
	.word z80cpu_ERROR		;42
	.word z80cpu_ERROR		;43
	.word z80cpu_LD_B_IXH		;44
	.word z80cpu_LD_B_IXL		;45
	.word z80cpu_LD_B_IIX_dI	;46
	.word z80cpu_ERROR		;47
	.word z80cpu_ERROR		;48
	.word z80cpu_ERROR		;49
	.word z80cpu_ERROR		;4A
	.word z80cpu_ERROR		;4B
	.word z80cpu_LD_C_IXH		;4C
	.word z80cpu_LD_C_IXL		;4D
	.word z80cpu_LD_C_IIX_dI	;4E
	.word z80cpu_ERROR		;4F
	.word z80cpu_ERROR		;50
	.word z80cpu_ERROR		;51
	.word z80cpu_ERROR		;52
	.word z80cpu_ERROR		;53
	.word z80cpu_LD_D_IXH		;54
	.word z80cpu_LD_D_IXL		;55
	.word z80cpu_LD_D_IIX_dI	;56
	.word z80cpu_ERROR		;57
	.word z80cpu_ERROR		;58
	.word z80cpu_ERROR		;59
	.word z80cpu_ERROR		;5A
	.word z80cpu_ERROR		;5B
	.word z80cpu_LD_E_IXH		;5C
	.word z80cpu_LD_E_IXL		;5D
	.word z80cpu_LD_E_IIX_dI	;5E
	.word z80cpu_ERROR		;5F
	.word z80cpu_LD_IXH_B		;60
	.word z80cpu_LD_IXH_C		;61
	.word z80cpu_LD_IXH_D		;62
	.word z80cpu_LD_IXH_E		;63
	.word z80cpu_LD_IXH_IXH		;64
	.word z80cpu_LD_IXH_IXL		;65
	.word z80cpu_LD_H_IIX_dI	;66
	.word z80cpu_LD_IXH_A		;67
	.word z80cpu_LD_IXL_B		;68
	.word z80cpu_LD_IXL_C		;69
	.word z80cpu_LD_IXL_D		;6A
	.word z80cpu_LD_IXL_E		;6B
	.word z80cpu_LD_IXL_IXH		;6C
	.word z80cpu_LD_IXL_IXL		;6D
	.word z80cpu_LD_L_IIX_dI	;6E
	.word z80cpu_LD_IXL_A		;6F
	.word z80cpu_LD_IIX_dI_B	;70
	.word z80cpu_LD_IIX_dI_C	;71
	.word z80cpu_LD_IIX_dI_D	;72
	.word z80cpu_LD_IIX_dI_E	;73
	.word z80cpu_LD_IIX_dI_H	;74
	.word z80cpu_LD_IIX_dI_L	;75
	.word z80cpu_ERROR		;76
	.word z80cpu_LD_IIX_dI_A	;77
	.word z80cpu_ERROR		;78
	.word z80cpu_ERROR		;79
	.word z80cpu_ERROR		;7A
	.word z80cpu_ERROR		;7B
	.word z80cpu_LD_A_IXH		;7C
	.word z80cpu_LD_A_IXL		;7D
	.word z80cpu_LD_A_IIX_dI	;7E
	.word z80cpu_ERROR		;7F
	.word z80cpu_ERROR		;80
	.word z80cpu_ERROR		;81
	.word z80cpu_ERROR		;82
	.word z80cpu_ERROR		;83
	.word z80cpu_ADD_A_IXH		;84
	.word z80cpu_ADD_A_IXL		;85
	.word z80cpu_ADD_A_IIX_dI	;86
	.word z80cpu_ERROR		;87
	.word z80cpu_ERROR		;88
	.word z80cpu_ERROR		;89
	.word z80cpu_ERROR		;8A
	.word z80cpu_ERROR		;8B
	.word z80cpu_ADC_A_IXH		;8C
	.word z80cpu_ADC_A_IXL		;8D
	.word z80cpu_ADC_A_IIX_dI	;8E
	.word z80cpu_ERROR		;8F
	.word z80cpu_ERROR		;90
	.word z80cpu_ERROR		;91
	.word z80cpu_ERROR		;92
	.word z80cpu_ERROR		;93
	.word z80cpu_SUB_IXH		;94
	.word z80cpu_SUB_IXL		;95
	.word z80cpu_SUB_IIX_dI		;96
	.word z80cpu_ERROR		;97
	.word z80cpu_ERROR		;98
	.word z80cpu_ERROR		;99
	.word z80cpu_ERROR		;9A
	.word z80cpu_ERROR		;9B
	.word z80cpu_SBC_A_IXH		;9C
	.word z80cpu_SBC_A_IXL		;9D
	.word z80cpu_SBC_A_IIX_dI	;9E
	.word z80cpu_ERROR		;9F
	.word z80cpu_ERROR		;A0
	.word z80cpu_ERROR		;A1
	.word z80cpu_ERROR		;A2
	.word z80cpu_ERROR		;A3
	.word z80cpu_AND_IXH		;A4
	.word z80cpu_AND_IXL		;A5
	.word z80cpu_AND_IIX_dI		;A6
	.word z80cpu_ERROR		;A7
	.word z80cpu_ERROR		;A8
	.word z80cpu_ERROR		;A9
	.word z80cpu_ERROR		;AA
	.word z80cpu_ERROR		;AB
	.word z80cpu_XOR_IXH		;AC
	.word z80cpu_XOR_IXL		;AD
	.word z80cpu_XOR_IIX_dI		;AE
	.word z80cpu_ERROR		;AF
	.word z80cpu_ERROR		;B0
	.word z80cpu_ERROR		;B1
	.word z80cpu_ERROR		;B2
	.word z80cpu_ERROR		;B3
	.word z80cpu_OR_IXH		;B4
	.word z80cpu_OR_IXL		;B5
	.word z80cpu_OR_IIX_dI		;B6
	.word z80cpu_ERROR		;B7
	.word z80cpu_ERROR		;B8
	.word z80cpu_ERROR		;B9
	.word z80cpu_ERROR		;BA
	.word z80cpu_ERROR		;BB
	.word z80cpu_CP_IXH		;BC
	.word z80cpu_CP_IXL		;BD
	.word z80cpu_CP_IIX_dI		;BE
	.word z80cpu_ERROR		;BF
	.word z80cpu_ERROR		;C0
	.word z80cpu_ERROR		;C1
	.word z80cpu_ERROR		;C2
	.word z80cpu_ERROR		;C3
	.word z80cpu_ERROR		;C4
	.word z80cpu_ERROR		;C5
	.word z80cpu_ERROR		;C6
	.word z80cpu_ERROR		;C7
	.word z80cpu_ERROR		;C8
	.word z80cpu_ERROR		;C9
	.word z80cpu_ERROR		;CA
	.word z80cpu_DDCB		;CB
	.word z80cpu_ERROR		;CC
	.word z80cpu_ERROR		;CD
	.word z80cpu_ERROR		;CE
	.word z80cpu_ERROR		;CF
	.word z80cpu_ERROR		;D0
	.word z80cpu_ERROR		;D1
	.word z80cpu_ERROR		;D2
	.word z80cpu_ERROR		;D3
	.word z80cpu_ERROR		;D4
	.word z80cpu_ERROR		;D5
	.word z80cpu_ERROR		;D6
	.word z80cpu_ERROR		;D7
	.word z80cpu_ERROR		;D8
	.word z80cpu_ERROR		;D9
	.word z80cpu_ERROR		;DA
	.word z80cpu_ERROR		;DB
	.word z80cpu_ERROR		;DC
	.word z80cpu_ERROR		;DD
	.word z80cpu_ERROR		;DE
	.word z80cpu_ERROR		;DF
	.word z80cpu_ERROR		;E0
	.word z80cpu_POP_IX		;E1
	.word z80cpu_ERROR		;E2
	.word z80cpu_EX_ISPI_IX		;E3
	.word z80cpu_ERROR		;E4
	.word z80cpu_PUSH_IX		;E5
	.word z80cpu_ERROR		;E6
	.word z80cpu_ERROR		;E7
	.word z80cpu_ERROR		;E8
	.word z80cpu_JP_IIXI		;E9
	.word z80cpu_ERROR		;EA
	.word z80cpu_ERROR		;EB
	.word z80cpu_ERROR		;EC
	.word z80cpu_ERROR		;ED
	.word z80cpu_ERROR		;EE
	.word z80cpu_ERROR		;EF
	.word z80cpu_ERROR		;F0
	.word z80cpu_ERROR		;F1
	.word z80cpu_ERROR		;F2
	.word z80cpu_ERROR		;F3
	.word z80cpu_ERROR		;F4
	.word z80cpu_ERROR		;F5
	.word z80cpu_ERROR		;F6
	.word z80cpu_ERROR		;F7
	.word z80cpu_ERROR		;F8
	.word z80cpu_LD_SP_IX		;F9
	.word z80cpu_ERROR		;FA
	.word z80cpu_ERROR		;FB
	.word z80cpu_ERROR		;FC
	.word z80cpu_ERROR		;FD
	.word z80cpu_ERROR		;FE
	.word z80cpu_ERROR		;FF

	.global z80cpu_FDops
z80cpu_FDops:
	.word z80cpu_ERROR		;00
	.word z80cpu_ERROR		;01
	.word z80cpu_ERROR		;02
	.word z80cpu_ERROR		;03
	.word z80cpu_ERROR		;04
	.word z80cpu_ERROR		;05
	.word z80cpu_ERROR		;06
	.word z80cpu_ERROR		;07
	.word z80cpu_ERROR		;08
	.word z80cpu_ADD_IY_BC		;09
	.word z80cpu_ERROR		;0A
	.word z80cpu_ERROR		;0B
	.word z80cpu_ERROR		;0C
	.word z80cpu_ERROR		;0D
	.word z80cpu_ERROR		;0E
	.word z80cpu_ERROR		;0F
	.word z80cpu_ERROR		;10
	.word z80cpu_ERROR		;11
	.word z80cpu_ERROR		;12
	.word z80cpu_ERROR		;13
	.word z80cpu_ERROR		;14
	.word z80cpu_ERROR		;15
	.word z80cpu_ERROR		;16
	.word z80cpu_ERROR		;17
	.word z80cpu_ERROR		;18
	.word z80cpu_ADD_IY_DE		;19
	.word z80cpu_ERROR		;1A
	.word z80cpu_ERROR		;1B
	.word z80cpu_ERROR		;1C
	.word z80cpu_ERROR		;1D
	.word z80cpu_ERROR		;1E
	.word z80cpu_ERROR		;1F
	.word z80cpu_ERROR		;20
	.word z80cpu_LD_IY_lm		;21
	.word z80cpu_LD_IlmI_IY		;22
	.word z80cpu_INC_IY		;23
	.word z80cpu_INC_IYH		;24
	.word z80cpu_DEC_IYH		;25
	.word z80cpu_LD_IYH_n		;26
	.word z80cpu_ERROR		;27
	.word z80cpu_ERROR		;28
	.word z80cpu_ADD_IY_IY		;29
	.word z80cpu_LD_IY_IlmI		;2A
	.word z80cpu_DEC_IY		;2B
	.word z80cpu_INC_IYL		;2C
	.word z80cpu_DEC_IYL		;2D
	.word z80cpu_LD_IYL_n		;2E
	.word z80cpu_ERROR		;2F
	.word z80cpu_ERROR		;30
	.word z80cpu_ERROR		;31
	.word z80cpu_ERROR		;32
	.word z80cpu_ERROR		;33
	.word z80cpu_INC_IIY_dI		;34
	.word z80cpu_DEC_IIY_dI		;35
	.word z80cpu_LD_IIY_dI_n	;36
	.word z80cpu_ERROR		;37
	.word z80cpu_ERROR		;38
	.word z80cpu_ADD_IY_SP		;39
	.word z80cpu_ERROR		;3A
	.word z80cpu_ERROR		;3B
	.word z80cpu_ERROR		;3C
	.word z80cpu_ERROR		;3D
	.word z80cpu_ERROR		;3E
	.word z80cpu_ERROR		;3F
	.word z80cpu_ERROR		;40
	.word z80cpu_ERROR		;41
	.word z80cpu_ERROR		;42
	.word z80cpu_ERROR		;43
	.word z80cpu_LD_B_IYH		;44
	.word z80cpu_LD_B_IYL		;45
	.word z80cpu_LD_B_IIY_dI	;46
	.word z80cpu_ERROR		;47
	.word z80cpu_ERROR		;48
	.word z80cpu_ERROR		;49
	.word z80cpu_ERROR		;4A
	.word z80cpu_ERROR		;4B
	.word z80cpu_LD_C_IYH		;4C
	.word z80cpu_LD_C_IYL		;4D
	.word z80cpu_LD_C_IIY_dI	;4E
	.word z80cpu_ERROR		;4F
	.word z80cpu_ERROR		;50
	.word z80cpu_ERROR		;51
	.word z80cpu_ERROR		;52
	.word z80cpu_ERROR		;53
	.word z80cpu_LD_D_IYH		;54
	.word z80cpu_LD_D_IYL		;55
	.word z80cpu_LD_D_IIY_dI	;56
	.word z80cpu_ERROR		;57
	.word z80cpu_ERROR		;58
	.word z80cpu_ERROR		;59
	.word z80cpu_ERROR		;5A
	.word z80cpu_ERROR		;5B
	.word z80cpu_LD_E_IYH		;5C
	.word z80cpu_LD_E_IYL		;5D
	.word z80cpu_LD_E_IIY_dI	;5E
	.word z80cpu_ERROR		;5F
	.word z80cpu_LD_IYH_B		;60
	.word z80cpu_LD_IYH_C		;61
	.word z80cpu_LD_IYH_D		;62
	.word z80cpu_LD_IYH_E		;63
	.word z80cpu_LD_IYH_IYH		;64
	.word z80cpu_LD_IYH_IYL		;65
	.word z80cpu_LD_H_IIY_dI	;66
	.word z80cpu_LD_IYH_A		;67
	.word z80cpu_LD_IYL_B		;68
	.word z80cpu_LD_IYL_C		;69
	.word z80cpu_LD_IYL_D		;6A
	.word z80cpu_LD_IYL_E		;6B
	.word z80cpu_LD_IYL_IYH		;6C
	.word z80cpu_LD_IYL_IYL		;6D
	.word z80cpu_LD_L_IIY_dI	;6E
	.word z80cpu_LD_IYL_A		;6F
	.word z80cpu_LD_IIY_dI_B	;70
	.word z80cpu_LD_IIY_dI_C	;71
	.word z80cpu_LD_IIY_dI_D	;72
	.word z80cpu_LD_IIY_dI_E	;73
	.word z80cpu_LD_IIY_dI_H	;74
	.word z80cpu_LD_IIY_dI_L	;75
	.word z80cpu_ERROR		;76
	.word z80cpu_LD_IIY_dI_A	;77
	.word z80cpu_ERROR		;78
	.word z80cpu_ERROR		;79
	.word z80cpu_ERROR		;7A
	.word z80cpu_ERROR		;7B
	.word z80cpu_LD_A_IYH		;7C
	.word z80cpu_LD_A_IYL		;7D
	.word z80cpu_LD_A_IIY_dI	;7E
	.word z80cpu_ERROR		;7F
	.word z80cpu_ERROR		;80
	.word z80cpu_ERROR		;81
	.word z80cpu_ERROR		;82
	.word z80cpu_ERROR		;83
	.word z80cpu_ADD_A_IYH		;84
	.word z80cpu_ADD_A_IYL		;85
	.word z80cpu_ADD_A_IIY_dI	;86
	.word z80cpu_ERROR		;87
	.word z80cpu_ERROR		;88
	.word z80cpu_ERROR		;89
	.word z80cpu_ERROR		;8A
	.word z80cpu_ERROR		;8B
	.word z80cpu_ADC_A_IYH		;8C
	.word z80cpu_ADC_A_IYL		;8D
	.word z80cpu_ADC_A_IIY_dI	;8E
	.word z80cpu_ERROR		;8F
	.word z80cpu_ERROR		;90
	.word z80cpu_ERROR		;91
	.word z80cpu_ERROR		;92
	.word z80cpu_ERROR		;93
	.word z80cpu_SUB_IYH		;94
	.word z80cpu_SUB_IYL		;95
	.word z80cpu_SUB_IIY_dI		;96
	.word z80cpu_ERROR		;97
	.word z80cpu_ERROR		;98
	.word z80cpu_ERROR		;99
	.word z80cpu_ERROR		;9A
	.word z80cpu_ERROR		;9B
	.word z80cpu_SBC_A_IYH		;9C
	.word z80cpu_SBC_A_IYL		;9D
	.word z80cpu_SBC_A_IIY_dI	;9E
	.word z80cpu_ERROR		;9F
	.word z80cpu_ERROR		;A0
	.word z80cpu_ERROR		;A1
	.word z80cpu_ERROR		;A2
	.word z80cpu_ERROR		;A3
	.word z80cpu_AND_IYH		;A4
	.word z80cpu_AND_IYL		;A5
	.word z80cpu_AND_IIY_dI		;A6
	.word z80cpu_ERROR		;A7
	.word z80cpu_ERROR		;A8
	.word z80cpu_ERROR		;A9
	.word z80cpu_ERROR		;AA
	.word z80cpu_ERROR		;AB
	.word z80cpu_XOR_IYH		;AC
	.word z80cpu_XOR_IYL		;AD
	.word z80cpu_XOR_IIY_dI		;AE
	.word z80cpu_ERROR		;AF
	.word z80cpu_ERROR		;B0
	.word z80cpu_ERROR		;B1
	.word z80cpu_ERROR		;B2
	.word z80cpu_ERROR		;B3
	.word z80cpu_OR_IYH		;B4
	.word z80cpu_OR_IYL		;B5
	.word z80cpu_OR_IIY_dI		;B6
	.word z80cpu_ERROR		;B7
	.word z80cpu_ERROR		;B8
	.word z80cpu_ERROR		;B9
	.word z80cpu_ERROR		;BA
	.word z80cpu_ERROR		;BB
	.word z80cpu_CP_IYH		;BC
	.word z80cpu_CP_IYL		;BD
	.word z80cpu_CP_IIY_dI		;BE
	.word z80cpu_ERROR		;BF
	.word z80cpu_ERROR		;C0
	.word z80cpu_ERROR		;C1
	.word z80cpu_ERROR		;C2
	.word z80cpu_ERROR		;C3
	.word z80cpu_ERROR		;C4
	.word z80cpu_ERROR		;C5
	.word z80cpu_ERROR		;C6
	.word z80cpu_ERROR		;C7
	.word z80cpu_ERROR		;C8
	.word z80cpu_ERROR		;C9
	.word z80cpu_ERROR		;CA
	.word z80cpu_FDCB		;CB
	.word z80cpu_ERROR		;CC
	.word z80cpu_ERROR		;CD
	.word z80cpu_ERROR		;CE
	.word z80cpu_ERROR		;CF
	.word z80cpu_ERROR		;D0
	.word z80cpu_ERROR		;D1
	.word z80cpu_ERROR		;D2
	.word z80cpu_ERROR		;D3
	.word z80cpu_ERROR		;D4
	.word z80cpu_ERROR		;D5
	.word z80cpu_ERROR		;D6
	.word z80cpu_ERROR		;D7
	.word z80cpu_ERROR		;D8
	.word z80cpu_ERROR		;D9
	.word z80cpu_ERROR		;DA
	.word z80cpu_ERROR		;DB
	.word z80cpu_ERROR		;DC
	.word z80cpu_ERROR		;DD
	.word z80cpu_ERROR		;DE
	.word z80cpu_ERROR		;DF
	.word z80cpu_ERROR		;E0
	.word z80cpu_POP_IY		;E1
	.word z80cpu_ERROR		;E2
	.word z80cpu_EX_ISPI_IY		;E3
	.word z80cpu_ERROR		;E4
	.word z80cpu_PUSH_IY		;E5
	.word z80cpu_ERROR		;E6
	.word z80cpu_ERROR		;E7
	.word z80cpu_ERROR		;E8
	.word z80cpu_JP_IIYI		;E9
	.word z80cpu_ERROR		;EA
	.word z80cpu_ERROR		;EB
	.word z80cpu_ERROR		;EC
	.word z80cpu_ERROR		;ED
	.word z80cpu_ERROR		;EE
	.word z80cpu_ERROR		;EF
	.word z80cpu_ERROR		;F0
	.word z80cpu_ERROR		;F1
	.word z80cpu_ERROR		;F2
	.word z80cpu_ERROR		;F3
	.word z80cpu_ERROR		;F4
	.word z80cpu_ERROR		;F5
	.word z80cpu_ERROR		;F6
	.word z80cpu_ERROR		;F7
	.word z80cpu_ERROR		;F8
	.word z80cpu_LD_SP_IY		;F9
	.word z80cpu_ERROR		;FA
	.word z80cpu_ERROR		;FB
	.word z80cpu_ERROR		;FC
	.word z80cpu_ERROR		;FD
	.word z80cpu_ERROR		;FE
	.word z80cpu_ERROR		;FF

	.global z80cpu_XXCBops
z80cpu_XXCBops:
	.word z80cpu_ERROR		;00
	.word z80cpu_ERROR		;01
	.word z80cpu_ERROR		;02
	.word z80cpu_ERROR		;03
	.word z80cpu_ERROR		;04
	.word z80cpu_ERROR		;05
	.word z80cpu_RLC_IaddrI		;06
	.word z80cpu_ERROR		;07
	.word z80cpu_ERROR		;08
	.word z80cpu_ERROR		;09
	.word z80cpu_ERROR		;0A
	.word z80cpu_ERROR		;0B
	.word z80cpu_ERROR		;0C
	.word z80cpu_ERROR		;0D
	.word z80cpu_RRC_IaddrI		;0E
	.word z80cpu_ERROR		;0F
	.word z80cpu_ERROR		;10
	.word z80cpu_ERROR		;11
	.word z80cpu_ERROR		;12
	.word z80cpu_ERROR		;13
	.word z80cpu_ERROR		;14
	.word z80cpu_ERROR		;15
	.word z80cpu_RL_IaddrI		;16
	.word z80cpu_ERROR		;17
	.word z80cpu_ERROR		;18
	.word z80cpu_ERROR		;19
	.word z80cpu_ERROR		;1A
	.word z80cpu_ERROR		;1B
	.word z80cpu_ERROR		;1C
	.word z80cpu_ERROR		;1D
	.word z80cpu_RR_IaddrI		;1E
	.word z80cpu_ERROR		;1F
	.word z80cpu_ERROR		;20
	.word z80cpu_ERROR		;21
	.word z80cpu_ERROR		;22
	.word z80cpu_ERROR		;23
	.word z80cpu_ERROR		;24
	.word z80cpu_ERROR		;25
	.word z80cpu_SLA_IaddrI		;26
	.word z80cpu_ERROR		;27
	.word z80cpu_ERROR		;28
	.word z80cpu_ERROR		;29
	.word z80cpu_ERROR		;2A
	.word z80cpu_ERROR		;2B
	.word z80cpu_ERROR		;2C
	.word z80cpu_ERROR		;2D
	.word z80cpu_SRA_IaddrI		;2E
	.word z80cpu_ERROR		;2F
	.word z80cpu_ERROR		;30
	.word z80cpu_ERROR		;31
	.word z80cpu_ERROR		;32
	.word z80cpu_ERROR		;33
	.word z80cpu_ERROR		;34
	.word z80cpu_ERROR		;35
	.word z80cpu_ERROR		;36
	.word z80cpu_ERROR		;37
	.word z80cpu_ERROR		;38
	.word z80cpu_ERROR		;39
	.word z80cpu_ERROR		;3A
	.word z80cpu_ERROR		;3B
	.word z80cpu_ERROR		;3C
	.word z80cpu_ERROR		;3D
	.word z80cpu_SRL_IaddrI		;3E
	.word z80cpu_ERROR		;3F
	.word z80cpu_ERROR		;40
	.word z80cpu_ERROR		;41
	.word z80cpu_ERROR		;42
	.word z80cpu_ERROR		;43
	.word z80cpu_ERROR		;44
	.word z80cpu_ERROR		;45
	.word z80cpu_BIT_0_IaddrI	;46
	.word z80cpu_ERROR		;47
	.word z80cpu_ERROR		;48
	.word z80cpu_ERROR		;49
	.word z80cpu_ERROR		;4A
	.word z80cpu_ERROR		;4B
	.word z80cpu_ERROR		;4C
	.word z80cpu_ERROR		;4D
	.word z80cpu_BIT_1_IaddrI	;4E
	.word z80cpu_ERROR		;4F
	.word z80cpu_ERROR		;50
	.word z80cpu_ERROR		;51
	.word z80cpu_ERROR		;52
	.word z80cpu_ERROR		;53
	.word z80cpu_ERROR		;54
	.word z80cpu_ERROR		;55
	.word z80cpu_BIT_2_IaddrI	;56
	.word z80cpu_ERROR		;57
	.word z80cpu_ERROR		;58
	.word z80cpu_ERROR		;59
	.word z80cpu_ERROR		;5A
	.word z80cpu_ERROR		;5B
	.word z80cpu_ERROR		;5C
	.word z80cpu_ERROR		;5D
	.word z80cpu_BIT_3_IaddrI	;5E
	.word z80cpu_ERROR		;5F
	.word z80cpu_ERROR		;60
	.word z80cpu_ERROR		;61
	.word z80cpu_ERROR		;62
	.word z80cpu_ERROR		;63
	.word z80cpu_ERROR		;64
	.word z80cpu_ERROR		;65
	.word z80cpu_BIT_4_IaddrI	;66
	.word z80cpu_ERROR		;67
	.word z80cpu_ERROR		;68
	.word z80cpu_ERROR		;69
	.word z80cpu_ERROR		;6A
	.word z80cpu_ERROR		;6B
	.word z80cpu_ERROR		;6C
	.word z80cpu_ERROR		;6D
	.word z80cpu_BIT_5_IaddrI	;6E
	.word z80cpu_ERROR		;6F
	.word z80cpu_ERROR		;70
	.word z80cpu_ERROR		;71
	.word z80cpu_ERROR		;72
	.word z80cpu_ERROR		;73
	.word z80cpu_ERROR		;74
	.word z80cpu_ERROR		;75
	.word z80cpu_BIT_6_IaddrI	;76
	.word z80cpu_ERROR		;77
	.word z80cpu_ERROR		;78
	.word z80cpu_ERROR		;79
	.word z80cpu_ERROR		;7A
	.word z80cpu_ERROR		;7B
	.word z80cpu_ERROR		;7C
	.word z80cpu_ERROR		;7D
	.word z80cpu_BIT_7_IaddrI	;7E
	.word z80cpu_ERROR		;7F
	.word z80cpu_ERROR		;80
	.word z80cpu_ERROR		;81
	.word z80cpu_ERROR		;82
	.word z80cpu_ERROR		;83
	.word z80cpu_ERROR		;84
	.word z80cpu_ERROR		;85
	.word z80cpu_RES_0_IaddrI	;86
	.word z80cpu_ERROR		;87
	.word z80cpu_ERROR		;88
	.word z80cpu_ERROR		;89
	.word z80cpu_ERROR		;8A
	.word z80cpu_ERROR		;8B
	.word z80cpu_ERROR		;8C
	.word z80cpu_ERROR		;8D
	.word z80cpu_RES_1_IaddrI	;8E
	.word z80cpu_ERROR		;8F
	.word z80cpu_ERROR		;90
	.word z80cpu_ERROR		;91
	.word z80cpu_ERROR		;92
	.word z80cpu_ERROR		;93
	.word z80cpu_ERROR		;94
	.word z80cpu_ERROR		;95
	.word z80cpu_RES_2_IaddrI	;96
	.word z80cpu_ERROR		;97
	.word z80cpu_ERROR		;98
	.word z80cpu_ERROR		;99
	.word z80cpu_ERROR		;9A
	.word z80cpu_ERROR		;9B
	.word z80cpu_ERROR		;9C
	.word z80cpu_ERROR		;9D
	.word z80cpu_RES_3_IaddrI	;9E
	.word z80cpu_ERROR		;9F
	.word z80cpu_ERROR		;A0
	.word z80cpu_ERROR		;A1
	.word z80cpu_ERROR		;A2
	.word z80cpu_ERROR		;A3
	.word z80cpu_ERROR		;A4
	.word z80cpu_ERROR		;A5
	.word z80cpu_RES_4_IaddrI	;A6
	.word z80cpu_ERROR		;A7
	.word z80cpu_ERROR		;A8
	.word z80cpu_ERROR		;A9
	.word z80cpu_ERROR		;AA
	.word z80cpu_ERROR		;AB
	.word z80cpu_ERROR		;AC
	.word z80cpu_ERROR		;AD
	.word z80cpu_RES_5_IaddrI	;AE
	.word z80cpu_ERROR		;AF
	.word z80cpu_ERROR		;B0
	.word z80cpu_ERROR		;B1
	.word z80cpu_ERROR		;B2
	.word z80cpu_ERROR		;B3
	.word z80cpu_ERROR		;B4
	.word z80cpu_ERROR		;B5
	.word z80cpu_RES_6_IaddrI	;B6
	.word z80cpu_ERROR		;B7
	.word z80cpu_ERROR		;B8
	.word z80cpu_ERROR		;B9
	.word z80cpu_ERROR		;BA
	.word z80cpu_ERROR		;BB
	.word z80cpu_ERROR		;BC
	.word z80cpu_ERROR		;BD
	.word z80cpu_RES_7_IaddrI	;BE
	.word z80cpu_ERROR		;BF
	.word z80cpu_ERROR		;C0
	.word z80cpu_ERROR		;C1
	.word z80cpu_ERROR		;C2
	.word z80cpu_ERROR		;C3
	.word z80cpu_ERROR		;C4
	.word z80cpu_ERROR		;C5
	.word z80cpu_SET_0_IaddrI	;C6
	.word z80cpu_ERROR		;C7
	.word z80cpu_ERROR		;C8
	.word z80cpu_ERROR		;C9
	.word z80cpu_ERROR		;CA
	.word z80cpu_ERROR		;CB
	.word z80cpu_ERROR		;CC
	.word z80cpu_ERROR		;CD
	.word z80cpu_SET_1_IaddrI	;CE
	.word z80cpu_ERROR		;CF
	.word z80cpu_ERROR		;D0
	.word z80cpu_ERROR		;D1
	.word z80cpu_ERROR		;D2
	.word z80cpu_ERROR		;D3
	.word z80cpu_ERROR		;D4
	.word z80cpu_ERROR		;D5
	.word z80cpu_SET_2_IaddrI	;D6
	.word z80cpu_ERROR		;D7
	.word z80cpu_ERROR		;D8
	.word z80cpu_ERROR		;D9
	.word z80cpu_ERROR		;DA
	.word z80cpu_ERROR		;DB
	.word z80cpu_ERROR		;DC
	.word z80cpu_ERROR		;DD
	.word z80cpu_SET_3_IaddrI	;DE
	.word z80cpu_ERROR		;DF
	.word z80cpu_ERROR		;E0
	.word z80cpu_ERROR		;E1
	.word z80cpu_ERROR		;E2
	.word z80cpu_ERROR		;E3
	.word z80cpu_ERROR		;E4
	.word z80cpu_ERROR		;E5
	.word z80cpu_SET_4_IaddrI	;E6
	.word z80cpu_ERROR		;E7
	.word z80cpu_ERROR		;E8
	.word z80cpu_ERROR		;E9
	.word z80cpu_ERROR		;EA
	.word z80cpu_ERROR		;EB
	.word z80cpu_ERROR		;EC
	.word z80cpu_ERROR		;ED
	.word z80cpu_SET_5_IaddrI	;EE
	.word z80cpu_ERROR		;EF
	.word z80cpu_ERROR		;F0
	.word z80cpu_ERROR		;F1
	.word z80cpu_ERROR		;F2
	.word z80cpu_ERROR		;F3
	.word z80cpu_ERROR		;F4
	.word z80cpu_ERROR		;F5
	.word z80cpu_SET_6_IaddrI	;F6
	.word z80cpu_ERROR		;F7
	.word z80cpu_ERROR		;F8
	.word z80cpu_ERROR		;F9
	.word z80cpu_ERROR		;FA
	.word z80cpu_ERROR		;FB
	.word z80cpu_ERROR		;FC
	.word z80cpu_ERROR		;FD
	.word z80cpu_SET_7_IaddrI	;FE
	.word z80cpu_ERROR		;FF

;****************************************************************************
;	
;****************************************************************************

	.code
	.align 1

;
;	* 無効命令処理ルーチンです。
;	- 実行コンテキスト内から呼ばれることを想定しています。
;	  すなわち、各レジスタには規定の値が保持されていなければいけません。
;	  (詳細は、clipz8ca.hを参照してください。)
;	- 実行コンテキストをZ80CPU構造体に書き戻して実行コンテキストを抜けた後、
;	  C言語版のエラー処理ルーチン本体(z80cpu_error())へジャンプします。
;	  z80cpu_error()は処理を返しません。
;
	.global z80cpu_ERROR
z80cpu_ERROR:
	call	z80cpu_leave	; 	xcall z80cpu_leave		; 実行コンテキストを書き戻します。
	ext	z80cpu_error@rm	; 	xjp z80cpu_error		; エラー処理ルーチン本体へジャンプします。
	jp	z80cpu_error@rl

;
;	* 保留割り込みの実行を検査します。
;	- 実行コンテキスト内から呼ばれることを想定しています。
;	  すなわち、各レジスタには規定の値が保持されていなければいけません。
;	  (詳細は、clipz8ca.hを参照してください。)
;	- 実行コンテキストをZ80CPU構造体に書き戻して実行コンテキストを抜けた後、
;	  C言語版の保留割り込み検査ルーチン本体(z80cpu_check_pending())を呼び出します。
;	  z80cpu_check_pending()が処理を返すと、再び実行コンテキストを読み込み、
;	  実行コンテキスト内へ復帰します。
;	  z80cpu_check_pending()はZ80CPU構造体の内容を変化させる可能性があるため、
;	  以上の手順を踏む必要があることに注意してください。
;
	.global z80cpu_CHECK_PENDING
z80cpu_CHECK_PENDING:
	call	z80cpu_leave	; 	xcall z80cpu_leave		; 実行コンテキストを書き戻します。
	ext	z80cpu_check_pending@rm	; 	xcall z80cpu_check_pending	; 保留割り込みの実行を検査します。
	call	z80cpu_check_pending@rl
	jp	z80cpu_enter	; 	xjp   z80cpu_enter		; 実行コンテキストを取り出します。

;
;	実行コンテキストを取り出し、実行コンテキスト内へ入ります。
;
	.global z80cpu_enter
z80cpu_enter:
	ext	z80cpu+0x0@h	; 	xld.w  %r4, z80cpu		; z80cpuアドレス(固定値)を保持します。
	ext	z80cpu+0x0@m
	ld.w	%r4,z80cpu+0x0@l
	ext	z80mem+0x0@h	; 	xld.w  %r5, z80mem		; z80memアドレス(固定値)を保持します。
	ext	z80mem+0x0@m
	ld.w	%r5,z80mem+0x0@l
	ext	0x1		; 	xld.ub %r0, [%r4+0x1]		; Aレジスタを取り出します。
	ld.ub	%r0,[%r4]
	ld.ub	%r1,[%r4]	; 	xld.ub %r1, [%r4+0x0]		; Fレジスタを取り出し、C33形式に変換します。
	ext z80cpu_f2psr@ah
	ext z80cpu_f2psr@al
	ld.ub  %r1, [%r1]
	ext	0x16		; 	xld.uh %r2, [%r4+0x16]		; PCを取り出し、ベースアドレスを足します。
	ld.uh	%r2,[%r4]
	add    %r2, %r5
	ext	0x20		; 	xld.w  %r3, [%r4+0x20]	; Cycleを取り出します。
	ld.w	%r3,[%r4]
	ret

;
;	実行コンテキストを書き戻し、実行コンテキストから抜けます。
;
	.global z80cpu_leave
z80cpu_leave:
	ext	0x1		; 	xld.b [%r4+0x1], %r0		; Aレジスタを書き戻します。
	ld.b	[%r4],%r0
	ext z80cpu_psr2f@ah		; FレジスタをZ80形式に変換し、書き戻します。
	ext z80cpu_psr2f@al
	ld.ub  %r12, [%r1]
	ld.b	[%r4],%r12	; 	xld.b [%r4+0x0], %r12
	ld.w   %r12, %r2			; PCのベースアドレスを引き、書き戻します。
	sub    %r12, %r5
	ext	0x16		; 	xld.h [%r4+0x16], %r12
	ld.h	[%r4],%r12
	ext	0x20		; 	xld.w [%r4+0x20], %r3	; Cycleを書き戻します。
	ld.w	[%r4],%r3
	ret

;****************************************************************************
;	8-Bit Load Group
;****************************************************************************

	.global z80cpu_LD_A_n
	.global z80cpu_LD_A_A
	.global z80cpu_LD_A_B
	.global z80cpu_LD_A_C
	.global z80cpu_LD_A_D
	.global z80cpu_LD_A_E
	.global z80cpu_LD_A_H
	.global z80cpu_LD_A_L
	.global z80cpu_LD_A_IXH
	.global z80cpu_LD_A_IXL
	.global z80cpu_LD_A_IYH
	.global z80cpu_LD_A_IYL
	.global z80cpu_LD_B_n
	.global z80cpu_LD_B_A
	.global z80cpu_LD_B_B
	.global z80cpu_LD_B_C
	.global z80cpu_LD_B_D
	.global z80cpu_LD_B_E
	.global z80cpu_LD_B_H
	.global z80cpu_LD_B_L
	.global z80cpu_LD_B_IXH
	.global z80cpu_LD_B_IXL
	.global z80cpu_LD_B_IYH
	.global z80cpu_LD_B_IYL
	.global z80cpu_LD_C_n
	.global z80cpu_LD_C_A
	.global z80cpu_LD_C_B
	.global z80cpu_LD_C_C
	.global z80cpu_LD_C_D
	.global z80cpu_LD_C_E
	.global z80cpu_LD_C_H
	.global z80cpu_LD_C_L
	.global z80cpu_LD_C_IXH
	.global z80cpu_LD_C_IXL
	.global z80cpu_LD_C_IYH
	.global z80cpu_LD_C_IYL
	.global z80cpu_LD_D_n
	.global z80cpu_LD_D_A
	.global z80cpu_LD_D_B
	.global z80cpu_LD_D_C
	.global z80cpu_LD_D_D
	.global z80cpu_LD_D_E
	.global z80cpu_LD_D_H
	.global z80cpu_LD_D_L
	.global z80cpu_LD_D_IXH
	.global z80cpu_LD_D_IXL
	.global z80cpu_LD_D_IYH
	.global z80cpu_LD_D_IYL
	.global z80cpu_LD_E_n
	.global z80cpu_LD_E_A
	.global z80cpu_LD_E_B
	.global z80cpu_LD_E_C
	.global z80cpu_LD_E_D
	.global z80cpu_LD_E_E
	.global z80cpu_LD_E_H
	.global z80cpu_LD_E_L
	.global z80cpu_LD_E_IXH
	.global z80cpu_LD_E_IXL
	.global z80cpu_LD_E_IYH
	.global z80cpu_LD_E_IYL
	.global z80cpu_LD_H_n
	.global z80cpu_LD_H_A
	.global z80cpu_LD_H_B
	.global z80cpu_LD_H_C
	.global z80cpu_LD_H_D
	.global z80cpu_LD_H_E
	.global z80cpu_LD_H_H
	.global z80cpu_LD_H_L
	.global z80cpu_LD_L_n
	.global z80cpu_LD_L_A
	.global z80cpu_LD_L_B
	.global z80cpu_LD_L_C
	.global z80cpu_LD_L_D
	.global z80cpu_LD_L_E
	.global z80cpu_LD_L_H
	.global z80cpu_LD_L_L
	.global z80cpu_LD_IXH_n
	.global z80cpu_LD_IXH_A
	.global z80cpu_LD_IXH_B
	.global z80cpu_LD_IXH_C
	.global z80cpu_LD_IXH_D
	.global z80cpu_LD_IXH_E
	.global z80cpu_LD_IXH_IXH
	.global z80cpu_LD_IXH_IXL
	.global z80cpu_LD_IXL_n
	.global z80cpu_LD_IXL_A
	.global z80cpu_LD_IXL_B
	.global z80cpu_LD_IXL_C
	.global z80cpu_LD_IXL_D
	.global z80cpu_LD_IXL_E
	.global z80cpu_LD_IXL_IXH
	.global z80cpu_LD_IXL_IXL
	.global z80cpu_LD_IYH_n
	.global z80cpu_LD_IYH_A
	.global z80cpu_LD_IYH_B
	.global z80cpu_LD_IYH_C
	.global z80cpu_LD_IYH_D
	.global z80cpu_LD_IYH_E
	.global z80cpu_LD_IYH_IYH
	.global z80cpu_LD_IYH_IYL
	.global z80cpu_LD_IYL_n
	.global z80cpu_LD_IYL_A
	.global z80cpu_LD_IYL_B
	.global z80cpu_LD_IYL_C
	.global z80cpu_LD_IYL_D
	.global z80cpu_LD_IYL_E
	.global z80cpu_LD_IYL_IYH
	.global z80cpu_LD_IYL_IYL

	.global z80cpu_LD_A_IlmI
	.global z80cpu_LD_A_IBCI
	.global z80cpu_LD_A_IDEI
	.global z80cpu_LD_A_IHLI
	.global z80cpu_LD_B_IHLI
	.global z80cpu_LD_C_IHLI
	.global z80cpu_LD_D_IHLI
	.global z80cpu_LD_E_IHLI
	.global z80cpu_LD_H_IHLI
	.global z80cpu_LD_L_IHLI
	.global z80cpu_LD_A_IIX_dI
	.global z80cpu_LD_B_IIX_dI
	.global z80cpu_LD_C_IIX_dI
	.global z80cpu_LD_D_IIX_dI
	.global z80cpu_LD_E_IIX_dI
	.global z80cpu_LD_H_IIX_dI
	.global z80cpu_LD_L_IIX_dI
	.global z80cpu_LD_A_IIY_dI
	.global z80cpu_LD_B_IIY_dI
	.global z80cpu_LD_C_IIY_dI
	.global z80cpu_LD_D_IIY_dI
	.global z80cpu_LD_E_IIY_dI
	.global z80cpu_LD_H_IIY_dI
	.global z80cpu_LD_L_IIY_dI

	.global z80cpu_LD_IlmI_A
	.global z80cpu_LD_IHLI_n
	.global z80cpu_LD_IBCI_A
	.global z80cpu_LD_IDEI_A
	.global z80cpu_LD_IHLI_A
	.global z80cpu_LD_IHLI_B
	.global z80cpu_LD_IHLI_C
	.global z80cpu_LD_IHLI_D
	.global z80cpu_LD_IHLI_E
	.global z80cpu_LD_IHLI_H
	.global z80cpu_LD_IHLI_L
	.global z80cpu_LD_IIX_dI_n
	.global z80cpu_LD_IIY_dI_n
	.global z80cpu_LD_IIX_dI_A
	.global z80cpu_LD_IIX_dI_B
	.global z80cpu_LD_IIX_dI_C
	.global z80cpu_LD_IIX_dI_D
	.global z80cpu_LD_IIX_dI_E
	.global z80cpu_LD_IIX_dI_H
	.global z80cpu_LD_IIX_dI_L
	.global z80cpu_LD_IIY_dI_A
	.global z80cpu_LD_IIY_dI_B
	.global z80cpu_LD_IIY_dI_C
	.global z80cpu_LD_IIY_dI_D
	.global z80cpu_LD_IIY_dI_E
	.global z80cpu_LD_IIY_dI_H
	.global z80cpu_LD_IIY_dI_L

	.global z80cpu_LD_A_I
	.global z80cpu_LD_A_R
	.global z80cpu_LD_I_A
	.global z80cpu_LD_R_A

;----------------------------------------------------------------------------

z80cpu_LD_A_n:
	ld.ub %r0, [%r2]+		; %A = n
	ret.d
	sub %r3, 7	; *delay*

z80cpu_LD_A_A:
	ld.w %r0, %r0			; %A = A
	ret.d
	sub %r3, 4	; *delay*

;#macro LD_A_r $1, $2
;	xld.ub %A, [%CPU+$2]		; %A = r
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_A_B:
	ext	0x3		; 	xld.ub %r0, [%r4+0x3]		; %A = r	; 	LD_A_r CYCLE_LD_A_B, B
	ld.ub	%r0,[%r4]
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_A_C:
	ext	0x2		; 	xld.ub %r0, [%r4+0x2]		; %A = r	; 	LD_A_r CYCLE_LD_A_C, C
	ld.ub	%r0,[%r4]
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_A_D:
	ext	0x5		; 	xld.ub %r0, [%r4+0x5]		; %A = r	; 	LD_A_r CYCLE_LD_A_D, D
	ld.ub	%r0,[%r4]
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_A_E:
	ext	0x4		; 	xld.ub %r0, [%r4+0x4]		; %A = r	; 	LD_A_r CYCLE_LD_A_E, E
	ld.ub	%r0,[%r4]
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_A_H:
	ext	0x7		; 	xld.ub %r0, [%r4+0x7]		; %A = r	; 	LD_A_r CYCLE_LD_A_H, H
	ld.ub	%r0,[%r4]
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_A_L:
	ext	0x6		; 	xld.ub %r0, [%r4+0x6]		; %A = r	; 	LD_A_r CYCLE_LD_A_L, L
	ld.ub	%r0,[%r4]
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_A_IXH:
	ext	0x11		; 	xld.ub %r0, [%r4+0x11]		; %A = r	; 	LD_A_r CYCLE_LD_A_IXH, IXH
	ld.ub	%r0,[%r4]
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_A_IXL:
	ext	0x10		; 	xld.ub %r0, [%r4+0x10]		; %A = r	; 	LD_A_r CYCLE_LD_A_IXL, IXL
	ld.ub	%r0,[%r4]
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_A_IYH:
	ext	0x13		; 	xld.ub %r0, [%r4+0x13]		; %A = r	; 	LD_A_r CYCLE_LD_A_IYH, IYH
	ld.ub	%r0,[%r4]
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_A_IYL:
	ext	0x12		; 	xld.ub %r0, [%r4+0x12]		; %A = r	; 	LD_A_r CYCLE_LD_A_IYL, IYL
	ld.ub	%r0,[%r4]
	ret.d
	sub %r3, 8			; *delay*

;#macro LD_r_n $1, $2
;	ld.ub  %t0, [%PC]+		; %t0 = n
;	xld.b [%CPU+$2], %t0		; r = n
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_B_n:
	ld.ub  %r12, [%r2]+		; %t0 = n	; 	LD_r_n CYCLE_LD_B_n, B
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = n
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_C_n:
	ld.ub  %r12, [%r2]+		; %t0 = n	; 	LD_r_n CYCLE_LD_C_n, C
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = n
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_D_n:
	ld.ub  %r12, [%r2]+		; %t0 = n	; 	LD_r_n CYCLE_LD_D_n, D
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = n
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_E_n:
	ld.ub  %r12, [%r2]+		; %t0 = n	; 	LD_r_n CYCLE_LD_E_n, E
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = n
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_H_n:
	ld.ub  %r12, [%r2]+		; %t0 = n	; 	LD_r_n CYCLE_LD_H_n, H
	ext	0x7		; 	xld.b [%r4+0x7], %r12		; r = n
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_L_n:
	ld.ub  %r12, [%r2]+		; %t0 = n	; 	LD_r_n CYCLE_LD_L_n, L
	ext	0x6		; 	xld.b [%r4+0x6], %r12		; r = n
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_IXH_n:
	ld.ub  %r12, [%r2]+		; %t0 = n	; 	LD_r_n CYCLE_LD_IXH_n, IXH
	ext	0x11		; 	xld.b [%r4+0x11], %r12		; r = n
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 11			; *delay*
z80cpu_LD_IXL_n:
	ld.ub  %r12, [%r2]+		; %t0 = n	; 	LD_r_n CYCLE_LD_IXL_n, IXL
	ext	0x10		; 	xld.b [%r4+0x10], %r12		; r = n
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 11			; *delay*
z80cpu_LD_IYH_n:
	ld.ub  %r12, [%r2]+		; %t0 = n	; 	LD_r_n CYCLE_LD_IYH_n, IYH
	ext	0x13		; 	xld.b [%r4+0x13], %r12		; r = n
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 11			; *delay*
z80cpu_LD_IYL_n:
	ld.ub  %r12, [%r2]+		; %t0 = n	; 	LD_r_n CYCLE_LD_IYL_n, IYL
	ext	0x12		; 	xld.b [%r4+0x12], %r12		; r = n
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 11			; *delay*

;#macro LD_r_A $1, $2
;	xld.b [%CPU+$2], %A		; r = A
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_B_A:
	ext	0x3		; 	xld.b [%r4+0x3], %r0		; r = A	; 	LD_r_A CYCLE_LD_B_A, B
	ld.b	[%r4],%r0
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_C_A:
	ext	0x2		; 	xld.b [%r4+0x2], %r0		; r = A	; 	LD_r_A CYCLE_LD_C_A, C
	ld.b	[%r4],%r0
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_D_A:
	ext	0x5		; 	xld.b [%r4+0x5], %r0		; r = A	; 	LD_r_A CYCLE_LD_D_A, D
	ld.b	[%r4],%r0
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_E_A:
	ext	0x4		; 	xld.b [%r4+0x4], %r0		; r = A	; 	LD_r_A CYCLE_LD_E_A, E
	ld.b	[%r4],%r0
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_H_A:
	ext	0x7		; 	xld.b [%r4+0x7], %r0		; r = A	; 	LD_r_A CYCLE_LD_H_A, H
	ld.b	[%r4],%r0
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_L_A:
	ext	0x6		; 	xld.b [%r4+0x6], %r0		; r = A	; 	LD_r_A CYCLE_LD_L_A, L
	ld.b	[%r4],%r0
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_IXH_A:
	ext	0x11		; 	xld.b [%r4+0x11], %r0		; r = A	; 	LD_r_A CYCLE_LD_IXH_A, IXH
	ld.b	[%r4],%r0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IXL_A:
	ext	0x10		; 	xld.b [%r4+0x10], %r0		; r = A	; 	LD_r_A CYCLE_LD_IXL_A, IXL
	ld.b	[%r4],%r0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IYH_A:
	ext	0x13		; 	xld.b [%r4+0x13], %r0		; r = A	; 	LD_r_A CYCLE_LD_IYH_A, IYH
	ld.b	[%r4],%r0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IYL_A:
	ext	0x12		; 	xld.b [%r4+0x12], %r0		; r = A	; 	LD_r_A CYCLE_LD_IYL_A, IYL
	ld.b	[%r4],%r0
	ret.d
	sub %r3, 8			; *delay*

;#macro LD_r_s $1, $2, $3
;	xld.ub %t0, [%CPU+$3]		; %t0 = s
;	xld.b [%CPU+$2], %t0		; r = s
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_B_B:
	ext	0x3		; 	xld.ub %r12, [%r4+0x3]		; %t0 = s	; 	LD_r_s CYCLE_LD_B_B, B, B
	ld.ub	%r12,[%r4]
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_B_C:
	ext	0x2		; 	xld.ub %r12, [%r4+0x2]		; %t0 = s	; 	LD_r_s CYCLE_LD_B_C, B, C
	ld.ub	%r12,[%r4]
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_B_D:
	ext	0x5		; 	xld.ub %r12, [%r4+0x5]		; %t0 = s	; 	LD_r_s CYCLE_LD_B_D, B, D
	ld.ub	%r12,[%r4]
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_B_E:
	ext	0x4		; 	xld.ub %r12, [%r4+0x4]		; %t0 = s	; 	LD_r_s CYCLE_LD_B_E, B, E
	ld.ub	%r12,[%r4]
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_B_H:
	ext	0x7		; 	xld.ub %r12, [%r4+0x7]		; %t0 = s	; 	LD_r_s CYCLE_LD_B_H, B, H
	ld.ub	%r12,[%r4]
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_B_L:
	ext	0x6		; 	xld.ub %r12, [%r4+0x6]		; %t0 = s	; 	LD_r_s CYCLE_LD_B_L, B, L
	ld.ub	%r12,[%r4]
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_B_IXH:
	ext	0x11		; 	xld.ub %r12, [%r4+0x11]		; %t0 = s	; 	LD_r_s CYCLE_LD_B_IXH, B, IXH
	ld.ub	%r12,[%r4]
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_B_IXL:
	ext	0x10		; 	xld.ub %r12, [%r4+0x10]		; %t0 = s	; 	LD_r_s CYCLE_LD_B_IXL, B, IXL
	ld.ub	%r12,[%r4]
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_B_IYH:
	ext	0x13		; 	xld.ub %r12, [%r4+0x13]		; %t0 = s	; 	LD_r_s CYCLE_LD_B_IYH, B, IYH
	ld.ub	%r12,[%r4]
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_B_IYL:
	ext	0x12		; 	xld.ub %r12, [%r4+0x12]		; %t0 = s	; 	LD_r_s CYCLE_LD_B_IYL, B, IYL
	ld.ub	%r12,[%r4]
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*

z80cpu_LD_C_B:
	ext	0x3		; 	xld.ub %r12, [%r4+0x3]		; %t0 = s	; 	LD_r_s CYCLE_LD_C_B, C, B
	ld.ub	%r12,[%r4]
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_C_C:
	ext	0x2		; 	xld.ub %r12, [%r4+0x2]		; %t0 = s	; 	LD_r_s CYCLE_LD_C_C, C, C
	ld.ub	%r12,[%r4]
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_C_D:
	ext	0x5		; 	xld.ub %r12, [%r4+0x5]		; %t0 = s	; 	LD_r_s CYCLE_LD_C_D, C, D
	ld.ub	%r12,[%r4]
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_C_E:
	ext	0x4		; 	xld.ub %r12, [%r4+0x4]		; %t0 = s	; 	LD_r_s CYCLE_LD_C_E, C, E
	ld.ub	%r12,[%r4]
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_C_H:
	ext	0x7		; 	xld.ub %r12, [%r4+0x7]		; %t0 = s	; 	LD_r_s CYCLE_LD_C_H, C, H
	ld.ub	%r12,[%r4]
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_C_L:
	ext	0x6		; 	xld.ub %r12, [%r4+0x6]		; %t0 = s	; 	LD_r_s CYCLE_LD_C_L, C, L
	ld.ub	%r12,[%r4]
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_C_IXH:
	ext	0x11		; 	xld.ub %r12, [%r4+0x11]		; %t0 = s	; 	LD_r_s CYCLE_LD_C_IXH, C, IXH
	ld.ub	%r12,[%r4]
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_C_IXL:
	ext	0x10		; 	xld.ub %r12, [%r4+0x10]		; %t0 = s	; 	LD_r_s CYCLE_LD_C_IXL, C, IXL
	ld.ub	%r12,[%r4]
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_C_IYH:
	ext	0x13		; 	xld.ub %r12, [%r4+0x13]		; %t0 = s	; 	LD_r_s CYCLE_LD_C_IYH, C, IYH
	ld.ub	%r12,[%r4]
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_C_IYL:
	ext	0x12		; 	xld.ub %r12, [%r4+0x12]		; %t0 = s	; 	LD_r_s CYCLE_LD_C_IYL, C, IYL
	ld.ub	%r12,[%r4]
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*

z80cpu_LD_D_B:
	ext	0x3		; 	xld.ub %r12, [%r4+0x3]		; %t0 = s	; 	LD_r_s CYCLE_LD_D_B, D, B
	ld.ub	%r12,[%r4]
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_D_C:
	ext	0x2		; 	xld.ub %r12, [%r4+0x2]		; %t0 = s	; 	LD_r_s CYCLE_LD_D_C, D, C
	ld.ub	%r12,[%r4]
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_D_D:
	ext	0x5		; 	xld.ub %r12, [%r4+0x5]		; %t0 = s	; 	LD_r_s CYCLE_LD_D_D, D, D
	ld.ub	%r12,[%r4]
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_D_E:
	ext	0x4		; 	xld.ub %r12, [%r4+0x4]		; %t0 = s	; 	LD_r_s CYCLE_LD_D_E, D, E
	ld.ub	%r12,[%r4]
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_D_H:
	ext	0x7		; 	xld.ub %r12, [%r4+0x7]		; %t0 = s	; 	LD_r_s CYCLE_LD_D_H, D, H
	ld.ub	%r12,[%r4]
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_D_L:
	ext	0x6		; 	xld.ub %r12, [%r4+0x6]		; %t0 = s	; 	LD_r_s CYCLE_LD_D_L, D, L
	ld.ub	%r12,[%r4]
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_D_IXH:
	ext	0x11		; 	xld.ub %r12, [%r4+0x11]		; %t0 = s	; 	LD_r_s CYCLE_LD_D_IXH, D, IXH
	ld.ub	%r12,[%r4]
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_D_IXL:
	ext	0x10		; 	xld.ub %r12, [%r4+0x10]		; %t0 = s	; 	LD_r_s CYCLE_LD_D_IXL, D, IXL
	ld.ub	%r12,[%r4]
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_D_IYH:
	ext	0x13		; 	xld.ub %r12, [%r4+0x13]		; %t0 = s	; 	LD_r_s CYCLE_LD_D_IYH, D, IYH
	ld.ub	%r12,[%r4]
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_D_IYL:
	ext	0x12		; 	xld.ub %r12, [%r4+0x12]		; %t0 = s	; 	LD_r_s CYCLE_LD_D_IYL, D, IYL
	ld.ub	%r12,[%r4]
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*

z80cpu_LD_E_B:
	ext	0x3		; 	xld.ub %r12, [%r4+0x3]		; %t0 = s	; 	LD_r_s CYCLE_LD_E_B, E, B
	ld.ub	%r12,[%r4]
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_E_C:
	ext	0x2		; 	xld.ub %r12, [%r4+0x2]		; %t0 = s	; 	LD_r_s CYCLE_LD_E_C, E, C
	ld.ub	%r12,[%r4]
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_E_D:
	ext	0x5		; 	xld.ub %r12, [%r4+0x5]		; %t0 = s	; 	LD_r_s CYCLE_LD_E_D, E, D
	ld.ub	%r12,[%r4]
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_E_E:
	ext	0x4		; 	xld.ub %r12, [%r4+0x4]		; %t0 = s	; 	LD_r_s CYCLE_LD_E_E, E, E
	ld.ub	%r12,[%r4]
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_E_H:
	ext	0x7		; 	xld.ub %r12, [%r4+0x7]		; %t0 = s	; 	LD_r_s CYCLE_LD_E_H, E, H
	ld.ub	%r12,[%r4]
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_E_L:
	ext	0x6		; 	xld.ub %r12, [%r4+0x6]		; %t0 = s	; 	LD_r_s CYCLE_LD_E_L, E, L
	ld.ub	%r12,[%r4]
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_E_IXH:
	ext	0x11		; 	xld.ub %r12, [%r4+0x11]		; %t0 = s	; 	LD_r_s CYCLE_LD_E_IXH, E, IXH
	ld.ub	%r12,[%r4]
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_E_IXL:
	ext	0x10		; 	xld.ub %r12, [%r4+0x10]		; %t0 = s	; 	LD_r_s CYCLE_LD_E_IXL, E, IXL
	ld.ub	%r12,[%r4]
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_E_IYH:
	ext	0x13		; 	xld.ub %r12, [%r4+0x13]		; %t0 = s	; 	LD_r_s CYCLE_LD_E_IYH, E, IYH
	ld.ub	%r12,[%r4]
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_E_IYL:
	ext	0x12		; 	xld.ub %r12, [%r4+0x12]		; %t0 = s	; 	LD_r_s CYCLE_LD_E_IYL, E, IYL
	ld.ub	%r12,[%r4]
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*

z80cpu_LD_H_B:
	ext	0x3		; 	xld.ub %r12, [%r4+0x3]		; %t0 = s	; 	LD_r_s CYCLE_LD_H_B, H, B
	ld.ub	%r12,[%r4]
	ext	0x7		; 	xld.b [%r4+0x7], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_H_C:
	ext	0x2		; 	xld.ub %r12, [%r4+0x2]		; %t0 = s	; 	LD_r_s CYCLE_LD_H_C, H, C
	ld.ub	%r12,[%r4]
	ext	0x7		; 	xld.b [%r4+0x7], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_H_D:
	ext	0x5		; 	xld.ub %r12, [%r4+0x5]		; %t0 = s	; 	LD_r_s CYCLE_LD_H_D, H, D
	ld.ub	%r12,[%r4]
	ext	0x7		; 	xld.b [%r4+0x7], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_H_E:
	ext	0x4		; 	xld.ub %r12, [%r4+0x4]		; %t0 = s	; 	LD_r_s CYCLE_LD_H_E, H, E
	ld.ub	%r12,[%r4]
	ext	0x7		; 	xld.b [%r4+0x7], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_H_H:
	ext	0x7		; 	xld.ub %r12, [%r4+0x7]		; %t0 = s	; 	LD_r_s CYCLE_LD_H_H, H, H
	ld.ub	%r12,[%r4]
	ext	0x7		; 	xld.b [%r4+0x7], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_H_L:
	ext	0x6		; 	xld.ub %r12, [%r4+0x6]		; %t0 = s	; 	LD_r_s CYCLE_LD_H_L, H, L
	ld.ub	%r12,[%r4]
	ext	0x7		; 	xld.b [%r4+0x7], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*

z80cpu_LD_L_B:
	ext	0x3		; 	xld.ub %r12, [%r4+0x3]		; %t0 = s	; 	LD_r_s CYCLE_LD_L_B, L, B
	ld.ub	%r12,[%r4]
	ext	0x6		; 	xld.b [%r4+0x6], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_L_C:
	ext	0x2		; 	xld.ub %r12, [%r4+0x2]		; %t0 = s	; 	LD_r_s CYCLE_LD_L_C, L, C
	ld.ub	%r12,[%r4]
	ext	0x6		; 	xld.b [%r4+0x6], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_L_D:
	ext	0x5		; 	xld.ub %r12, [%r4+0x5]		; %t0 = s	; 	LD_r_s CYCLE_LD_L_D, L, D
	ld.ub	%r12,[%r4]
	ext	0x6		; 	xld.b [%r4+0x6], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_L_E:
	ext	0x4		; 	xld.ub %r12, [%r4+0x4]		; %t0 = s	; 	LD_r_s CYCLE_LD_L_E, L, E
	ld.ub	%r12,[%r4]
	ext	0x6		; 	xld.b [%r4+0x6], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_L_H:
	ext	0x7		; 	xld.ub %r12, [%r4+0x7]		; %t0 = s	; 	LD_r_s CYCLE_LD_L_H, L, H
	ld.ub	%r12,[%r4]
	ext	0x6		; 	xld.b [%r4+0x6], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*
z80cpu_LD_L_L:
	ext	0x6		; 	xld.ub %r12, [%r4+0x6]		; %t0 = s	; 	LD_r_s CYCLE_LD_L_L, L, L
	ld.ub	%r12,[%r4]
	ext	0x6		; 	xld.b [%r4+0x6], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 4			; *delay*

z80cpu_LD_IXH_B:
	ext	0x3		; 	xld.ub %r12, [%r4+0x3]		; %t0 = s	; 	LD_r_s CYCLE_LD_IXH_B, IXH, B
	ld.ub	%r12,[%r4]
	ext	0x11		; 	xld.b [%r4+0x11], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IXH_C:
	ext	0x2		; 	xld.ub %r12, [%r4+0x2]		; %t0 = s	; 	LD_r_s CYCLE_LD_IXH_C, IXH, C
	ld.ub	%r12,[%r4]
	ext	0x11		; 	xld.b [%r4+0x11], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IXH_D:
	ext	0x5		; 	xld.ub %r12, [%r4+0x5]		; %t0 = s	; 	LD_r_s CYCLE_LD_IXH_D, IXH, D
	ld.ub	%r12,[%r4]
	ext	0x11		; 	xld.b [%r4+0x11], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IXH_E:
	ext	0x4		; 	xld.ub %r12, [%r4+0x4]		; %t0 = s	; 	LD_r_s CYCLE_LD_IXH_E, IXH, E
	ld.ub	%r12,[%r4]
	ext	0x11		; 	xld.b [%r4+0x11], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IXH_IXH:
	ext	0x11		; 	xld.ub %r12, [%r4+0x11]		; %t0 = s	; 	LD_r_s CYCLE_LD_IXH_IXH, IXH, IXH
	ld.ub	%r12,[%r4]
	ext	0x11		; 	xld.b [%r4+0x11], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IXH_IXL:
	ext	0x10		; 	xld.ub %r12, [%r4+0x10]		; %t0 = s	; 	LD_r_s CYCLE_LD_IXH_IXL, IXH, IXL
	ld.ub	%r12,[%r4]
	ext	0x11		; 	xld.b [%r4+0x11], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*

z80cpu_LD_IXL_B:
	ext	0x3		; 	xld.ub %r12, [%r4+0x3]		; %t0 = s	; 	LD_r_s CYCLE_LD_IXL_B, IXL, B
	ld.ub	%r12,[%r4]
	ext	0x10		; 	xld.b [%r4+0x10], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IXL_C:
	ext	0x2		; 	xld.ub %r12, [%r4+0x2]		; %t0 = s	; 	LD_r_s CYCLE_LD_IXL_C, IXL, C
	ld.ub	%r12,[%r4]
	ext	0x10		; 	xld.b [%r4+0x10], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IXL_D:
	ext	0x5		; 	xld.ub %r12, [%r4+0x5]		; %t0 = s	; 	LD_r_s CYCLE_LD_IXL_D, IXL, D
	ld.ub	%r12,[%r4]
	ext	0x10		; 	xld.b [%r4+0x10], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IXL_E:
	ext	0x4		; 	xld.ub %r12, [%r4+0x4]		; %t0 = s	; 	LD_r_s CYCLE_LD_IXL_E, IXL, E
	ld.ub	%r12,[%r4]
	ext	0x10		; 	xld.b [%r4+0x10], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IXL_IXH:
	ext	0x11		; 	xld.ub %r12, [%r4+0x11]		; %t0 = s	; 	LD_r_s CYCLE_LD_IXL_IXH, IXL, IXH
	ld.ub	%r12,[%r4]
	ext	0x10		; 	xld.b [%r4+0x10], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IXL_IXL:
	ext	0x10		; 	xld.ub %r12, [%r4+0x10]		; %t0 = s	; 	LD_r_s CYCLE_LD_IXL_IXL, IXL, IXL
	ld.ub	%r12,[%r4]
	ext	0x10		; 	xld.b [%r4+0x10], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*

z80cpu_LD_IYH_B:
	ext	0x3		; 	xld.ub %r12, [%r4+0x3]		; %t0 = s	; 	LD_r_s CYCLE_LD_IYH_B, IYH, B
	ld.ub	%r12,[%r4]
	ext	0x13		; 	xld.b [%r4+0x13], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IYH_C:
	ext	0x2		; 	xld.ub %r12, [%r4+0x2]		; %t0 = s	; 	LD_r_s CYCLE_LD_IYH_C, IYH, C
	ld.ub	%r12,[%r4]
	ext	0x13		; 	xld.b [%r4+0x13], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IYH_D:
	ext	0x5		; 	xld.ub %r12, [%r4+0x5]		; %t0 = s	; 	LD_r_s CYCLE_LD_IYH_D, IYH, D
	ld.ub	%r12,[%r4]
	ext	0x13		; 	xld.b [%r4+0x13], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IYH_E:
	ext	0x4		; 	xld.ub %r12, [%r4+0x4]		; %t0 = s	; 	LD_r_s CYCLE_LD_IYH_E, IYH, E
	ld.ub	%r12,[%r4]
	ext	0x13		; 	xld.b [%r4+0x13], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IYH_IYH:
	ext	0x13		; 	xld.ub %r12, [%r4+0x13]		; %t0 = s	; 	LD_r_s CYCLE_LD_IYH_IYH, IYH, IYH
	ld.ub	%r12,[%r4]
	ext	0x13		; 	xld.b [%r4+0x13], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IYH_IYL:
	ext	0x12		; 	xld.ub %r12, [%r4+0x12]		; %t0 = s	; 	LD_r_s CYCLE_LD_IYH_IYL, IYH, IYL
	ld.ub	%r12,[%r4]
	ext	0x13		; 	xld.b [%r4+0x13], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*

z80cpu_LD_IYL_B:
	ext	0x3		; 	xld.ub %r12, [%r4+0x3]		; %t0 = s	; 	LD_r_s CYCLE_LD_IYL_B, IYL, B
	ld.ub	%r12,[%r4]
	ext	0x12		; 	xld.b [%r4+0x12], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IYL_C:
	ext	0x2		; 	xld.ub %r12, [%r4+0x2]		; %t0 = s	; 	LD_r_s CYCLE_LD_IYL_C, IYL, C
	ld.ub	%r12,[%r4]
	ext	0x12		; 	xld.b [%r4+0x12], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IYL_D:
	ext	0x5		; 	xld.ub %r12, [%r4+0x5]		; %t0 = s	; 	LD_r_s CYCLE_LD_IYL_D, IYL, D
	ld.ub	%r12,[%r4]
	ext	0x12		; 	xld.b [%r4+0x12], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IYL_E:
	ext	0x4		; 	xld.ub %r12, [%r4+0x4]		; %t0 = s	; 	LD_r_s CYCLE_LD_IYL_E, IYL, E
	ld.ub	%r12,[%r4]
	ext	0x12		; 	xld.b [%r4+0x12], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IYL_IYH:
	ext	0x13		; 	xld.ub %r12, [%r4+0x13]		; %t0 = s	; 	LD_r_s CYCLE_LD_IYL_IYH, IYL, IYH
	ld.ub	%r12,[%r4]
	ext	0x12		; 	xld.b [%r4+0x12], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*
z80cpu_LD_IYL_IYL:
	ext	0x12		; 	xld.ub %r12, [%r4+0x12]		; %t0 = s	; 	LD_r_s CYCLE_LD_IYL_IYL, IYL, IYL
	ld.ub	%r12,[%r4]
	ext	0x12		; 	xld.b [%r4+0x12], %r12		; r = s
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8			; *delay*

;----------------------------------------------------------------------------

z80cpu_LD_A_IlmI:
	ld.ub %r12, [%r2]+		; %t0 = m
	ld.ub %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll  %r13, 8			; %t0 = lm
	or    %r12, %r13
	add   %r12, %r5			; %t0 = mem+lm
	ld.ub %r0, [%r12]			; %A = [mem+lm]
	ret.d
	sub %r3, 13	; *delay*

;#macro LD_A_IrrI $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	add    %t0, %MEM		; %t0 = mem+rr
;	ld.ub  %A, [%t0]		; %A = [mem+rr]
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_A_IBCI:
	ext	0x2		; 	xld.uh %r12, [%r4+0x2]		; %t0 = rr	; 	LD_A_IrrI CYCLE_LD_A_IBCI, BC
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+rr
	ld.ub  %r0, [%r12]		; %A = [mem+rr]
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_A_IDEI:
	ext	0x4		; 	xld.uh %r12, [%r4+0x4]		; %t0 = rr	; 	LD_A_IrrI CYCLE_LD_A_IDEI, DE
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+rr
	ld.ub  %r0, [%r12]		; %A = [mem+rr]
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_A_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = rr	; 	LD_A_IrrI CYCLE_LD_A_IHLI, HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+rr
	ld.ub  %r0, [%r12]		; %A = [mem+rr]
	ret.d
	sub %r3, 7			; *delay*

;#macro LD_r_IHLI $1, $2
;	xld.uh %t0, [%CPU+HL]		; %t0 = HL
;	add    %t0, %MEM		; %t0 = mem+HL
;	ld.ub  %t0, [%t0]		; %t0 = [mem+HL]
;	xld.b [%CPU+$2], %t0		; r = [mem+HL]
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_B_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	LD_r_IHLI CYCLE_LD_B_IHLI, B
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r12, [%r12]		; %t0 = [mem+HL]
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = [mem+HL]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_C_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	LD_r_IHLI CYCLE_LD_C_IHLI, C
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r12, [%r12]		; %t0 = [mem+HL]
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = [mem+HL]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_D_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	LD_r_IHLI CYCLE_LD_D_IHLI, D
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r12, [%r12]		; %t0 = [mem+HL]
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = [mem+HL]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_E_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	LD_r_IHLI CYCLE_LD_E_IHLI, E
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r12, [%r12]		; %t0 = [mem+HL]
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = [mem+HL]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_H_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	LD_r_IHLI CYCLE_LD_H_IHLI, H
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r12, [%r12]		; %t0 = [mem+HL]
	ext	0x7		; 	xld.b [%r4+0x7], %r12		; r = [mem+HL]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_L_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	LD_r_IHLI CYCLE_LD_L_IHLI, L
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r12, [%r12]		; %t0 = [mem+HL]
	ext	0x6		; 	xld.b [%r4+0x6], %r12		; r = [mem+HL]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 7			; *delay*

;#macro LD_A_Irr_dI $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	ld.b   %t1, [%PC]+		; %t1 = d (signed)
;	add    %t0, %t1			; %t0 = rr+d
;	add    %t0, %MEM		; %t0 = mem+rr+d
;	ld.ub  %A, [%t0]		; %A = [mem+rr+d]
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_A_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	LD_A_Irr_dI CYCLE_LD_A_IIX_dI, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r0, [%r12]		; %A = [mem+rr+d]
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_A_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	LD_A_Irr_dI CYCLE_LD_A_IIY_dI, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r0, [%r12]		; %A = [mem+rr+d]
	ret.d
	sub %r3, 19			; *delay*

;#macro LD_r_Iss_dI $1, $2, $3
;	xld.uh %t0, [%CPU+$3]		; %t0 = ss
;	ld.b   %t1, [%PC]+		; %t1 = d (signed)
;	add    %t0, %t1			; %t0 = ss+d
;	add    %t0, %MEM		; %t0 = mem+ss+d
;	ld.ub  %t0, [%t0]		; %t0 = [mem+ss+d]
;	xld.b [%CPU+$2], %t0		; r = [mem+ss+d]
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_B_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = ss	; 	LD_r_Iss_dI CYCLE_LD_B_IIX_dI, B, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = ss+d
	add    %r12, %r5		; %t0 = mem+ss+d
	ld.ub  %r12, [%r12]		; %t0 = [mem+ss+d]
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = [mem+ss+d]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_C_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = ss	; 	LD_r_Iss_dI CYCLE_LD_C_IIX_dI, C, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = ss+d
	add    %r12, %r5		; %t0 = mem+ss+d
	ld.ub  %r12, [%r12]		; %t0 = [mem+ss+d]
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = [mem+ss+d]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_D_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = ss	; 	LD_r_Iss_dI CYCLE_LD_D_IIX_dI, D, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = ss+d
	add    %r12, %r5		; %t0 = mem+ss+d
	ld.ub  %r12, [%r12]		; %t0 = [mem+ss+d]
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = [mem+ss+d]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_E_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = ss	; 	LD_r_Iss_dI CYCLE_LD_E_IIX_dI, E, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = ss+d
	add    %r12, %r5		; %t0 = mem+ss+d
	ld.ub  %r12, [%r12]		; %t0 = [mem+ss+d]
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = [mem+ss+d]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_H_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = ss	; 	LD_r_Iss_dI CYCLE_LD_H_IIX_dI, H, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = ss+d
	add    %r12, %r5		; %t0 = mem+ss+d
	ld.ub  %r12, [%r12]		; %t0 = [mem+ss+d]
	ext	0x7		; 	xld.b [%r4+0x7], %r12		; r = [mem+ss+d]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_L_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = ss	; 	LD_r_Iss_dI CYCLE_LD_L_IIX_dI, L, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = ss+d
	add    %r12, %r5		; %t0 = mem+ss+d
	ld.ub  %r12, [%r12]		; %t0 = [mem+ss+d]
	ext	0x6		; 	xld.b [%r4+0x6], %r12		; r = [mem+ss+d]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 19			; *delay*

z80cpu_LD_B_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = ss	; 	LD_r_Iss_dI CYCLE_LD_B_IIY_dI, B, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = ss+d
	add    %r12, %r5		; %t0 = mem+ss+d
	ld.ub  %r12, [%r12]		; %t0 = [mem+ss+d]
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; r = [mem+ss+d]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_C_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = ss	; 	LD_r_Iss_dI CYCLE_LD_C_IIY_dI, C, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = ss+d
	add    %r12, %r5		; %t0 = mem+ss+d
	ld.ub  %r12, [%r12]		; %t0 = [mem+ss+d]
	ext	0x2		; 	xld.b [%r4+0x2], %r12		; r = [mem+ss+d]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_D_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = ss	; 	LD_r_Iss_dI CYCLE_LD_D_IIY_dI, D, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = ss+d
	add    %r12, %r5		; %t0 = mem+ss+d
	ld.ub  %r12, [%r12]		; %t0 = [mem+ss+d]
	ext	0x5		; 	xld.b [%r4+0x5], %r12		; r = [mem+ss+d]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_E_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = ss	; 	LD_r_Iss_dI CYCLE_LD_E_IIY_dI, E, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = ss+d
	add    %r12, %r5		; %t0 = mem+ss+d
	ld.ub  %r12, [%r12]		; %t0 = [mem+ss+d]
	ext	0x4		; 	xld.b [%r4+0x4], %r12		; r = [mem+ss+d]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_H_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = ss	; 	LD_r_Iss_dI CYCLE_LD_H_IIY_dI, H, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = ss+d
	add    %r12, %r5		; %t0 = mem+ss+d
	ld.ub  %r12, [%r12]		; %t0 = [mem+ss+d]
	ext	0x7		; 	xld.b [%r4+0x7], %r12		; r = [mem+ss+d]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_L_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = ss	; 	LD_r_Iss_dI CYCLE_LD_L_IIY_dI, L, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = ss+d
	add    %r12, %r5		; %t0 = mem+ss+d
	ld.ub  %r12, [%r12]		; %t0 = [mem+ss+d]
	ext	0x6		; 	xld.b [%r4+0x6], %r12		; r = [mem+ss+d]
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 19			; *delay*

;----------------------------------------------------------------------------

z80cpu_LD_IlmI_A:
	ld.ub %r12, [%r2]+		; %t0 = m
	ld.ub %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll  %r13, 8			; %t0 = lm
	or    %r12, %r13
	add   %r12, %r5			; %t0 = mem+lm
	ld.b [%r12], %r0			; [mem+lm] = A
	ret.d
	sub %r3, 13	; *delay*

z80cpu_LD_IHLI_n:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r13, [%r2]+		; %t1 = n
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+HL] = n
	ret.d
	sub %r3, 10	; *delay*

;#macro LD_IrrI_A $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	add    %t0, %MEM		; %t0 = mem+rr
;	xld.b [%t0], %A			; [mem+rr] = A
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_IBCI_A:
	ext	0x2		; 	xld.uh %r12, [%r4+0x2]		; %t0 = rr	; 	LD_IrrI_A CYCLE_LD_IBCI_A, BC
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+rr
	ld.b	[%r12],%r0	; 	xld.b [%r12], %r0			; [mem+rr] = A
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_IDEI_A:
	ext	0x4		; 	xld.uh %r12, [%r4+0x4]		; %t0 = rr	; 	LD_IrrI_A CYCLE_LD_IDEI_A, DE
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+rr
	ld.b	[%r12],%r0	; 	xld.b [%r12], %r0			; [mem+rr] = A
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_IHLI_A:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = rr	; 	LD_IrrI_A CYCLE_LD_IHLI_A, HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+rr
	ld.b	[%r12],%r0	; 	xld.b [%r12], %r0			; [mem+rr] = A
	ret.d
	sub %r3, 7			; *delay*

;#macro LD_IHLI_r $1, $2
;	xld.uh %t0, [%CPU+HL]		; %t0 = HL
;	add    %t0, %MEM		; %t0 = mem+HL
;	xld.ub %t1, [%CPU+$2]		; %t1 = r
;	xld.b [%t0], %t1		; [mem+HL] = r
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_IHLI_B:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	LD_IHLI_r CYCLE_LD_IHLI_B, B
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ext	0x3		; 	xld.ub %r13, [%r4+0x3]		; %t1 = r
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+HL] = r
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_IHLI_C:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	LD_IHLI_r CYCLE_LD_IHLI_C, C
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ext	0x2		; 	xld.ub %r13, [%r4+0x2]		; %t1 = r
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+HL] = r
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_IHLI_D:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	LD_IHLI_r CYCLE_LD_IHLI_D, D
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ext	0x5		; 	xld.ub %r13, [%r4+0x5]		; %t1 = r
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+HL] = r
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_IHLI_E:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	LD_IHLI_r CYCLE_LD_IHLI_E, E
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ext	0x4		; 	xld.ub %r13, [%r4+0x4]		; %t1 = r
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+HL] = r
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_IHLI_H:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	LD_IHLI_r CYCLE_LD_IHLI_H, H
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ext	0x7		; 	xld.ub %r13, [%r4+0x7]		; %t1 = r
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+HL] = r
	ret.d
	sub %r3, 7			; *delay*
z80cpu_LD_IHLI_L:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	LD_IHLI_r CYCLE_LD_IHLI_L, L
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ext	0x6		; 	xld.ub %r13, [%r4+0x6]		; %t1 = r
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+HL] = r
	ret.d
	sub %r3, 7			; *delay*

;#macro LD_Irr_dI_n $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	ld.b   %t1, [%PC]+		; %t1 = d (signed)
;	add    %t0, %t1			; %t0 = rr+d
;	add    %t0, %MEM		; %t0 = mem+rr+d
;	ld.ub  %t1, [%PC]+		; %t1 = n
;	xld.b [%t0], %t1		; [mem+rr+d] = n
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_IIX_dI_n:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	LD_Irr_dI_n CYCLE_LD_IIX_dI_n, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r13, [%r2]+		; %t1 = n
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = n
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_IIY_dI_n:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	LD_Irr_dI_n CYCLE_LD_IIY_dI_n, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r13, [%r2]+		; %t1 = n
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = n
	ret.d
	sub %r3, 19			; *delay*

;#macro LD_Irr_dI_A $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	ld.b   %t1, [%PC]+		; %t1 = d (signed)
;	add    %t0, %t1			; %t0 = rr+d
;	add    %t0, %MEM		; %t0 = mem+rr+d
;	xld.b [%t0], %A			; [mem+rr+d] = A
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_IIX_dI_A:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	LD_Irr_dI_A CYCLE_LD_IIX_dI_A, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.b	[%r12],%r0	; 	xld.b [%r12], %r0			; [mem+rr+d] = A
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_IIY_dI_A:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	LD_Irr_dI_A CYCLE_LD_IIY_dI_A, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.b	[%r12],%r0	; 	xld.b [%r12], %r0			; [mem+rr+d] = A
	ret.d
	sub %r3, 19			; *delay*

;#macro LD_Irr_dI_s $1, $2, $3
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	ld.b   %t1, [%PC]+		; %t1 = d (signed)
;	add    %t0, %t1			; %t0 = rr+d
;	add    %t0, %MEM		; %t0 = mem+rr+d
;	xld.ub %t1, [%CPU+$3]		; %t1 = s
;	xld.b [%t0], %t1		; [mem+rr+d] = s
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_IIX_dI_B:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	LD_Irr_dI_s CYCLE_LD_IIX_dI_B, IX, B
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ext	0x3		; 	xld.ub %r13, [%r4+0x3]		; %t1 = s
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = s
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_IIX_dI_C:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	LD_Irr_dI_s CYCLE_LD_IIX_dI_C, IX, C
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ext	0x2		; 	xld.ub %r13, [%r4+0x2]		; %t1 = s
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = s
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_IIX_dI_D:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	LD_Irr_dI_s CYCLE_LD_IIX_dI_D, IX, D
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ext	0x5		; 	xld.ub %r13, [%r4+0x5]		; %t1 = s
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = s
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_IIX_dI_E:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	LD_Irr_dI_s CYCLE_LD_IIX_dI_E, IX, E
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ext	0x4		; 	xld.ub %r13, [%r4+0x4]		; %t1 = s
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = s
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_IIX_dI_H:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	LD_Irr_dI_s CYCLE_LD_IIX_dI_H, IX, H
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ext	0x7		; 	xld.ub %r13, [%r4+0x7]		; %t1 = s
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = s
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_IIX_dI_L:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	LD_Irr_dI_s CYCLE_LD_IIX_dI_L, IX, L
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ext	0x6		; 	xld.ub %r13, [%r4+0x6]		; %t1 = s
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = s
	ret.d
	sub %r3, 19			; *delay*

z80cpu_LD_IIY_dI_B:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	LD_Irr_dI_s CYCLE_LD_IIY_dI_B, IY, B
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ext	0x3		; 	xld.ub %r13, [%r4+0x3]		; %t1 = s
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = s
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_IIY_dI_C:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	LD_Irr_dI_s CYCLE_LD_IIY_dI_C, IY, C
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ext	0x2		; 	xld.ub %r13, [%r4+0x2]		; %t1 = s
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = s
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_IIY_dI_D:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	LD_Irr_dI_s CYCLE_LD_IIY_dI_D, IY, D
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ext	0x5		; 	xld.ub %r13, [%r4+0x5]		; %t1 = s
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = s
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_IIY_dI_E:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	LD_Irr_dI_s CYCLE_LD_IIY_dI_E, IY, E
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ext	0x4		; 	xld.ub %r13, [%r4+0x4]		; %t1 = s
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = s
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_IIY_dI_H:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	LD_Irr_dI_s CYCLE_LD_IIY_dI_H, IY, H
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ext	0x7		; 	xld.ub %r13, [%r4+0x7]		; %t1 = s
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = s
	ret.d
	sub %r3, 19			; *delay*
z80cpu_LD_IIY_dI_L:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	LD_Irr_dI_s CYCLE_LD_IIY_dI_L, IY, L
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ext	0x6		; 	xld.ub %r13, [%r4+0x6]		; %t1 = s
	ld.ub	%r13,[%r4]
	ld.b	[%r12],%r13	; 	xld.b [%r12], %r13		; [mem+rr+d] = s
	ret.d
	sub %r3, 19			; *delay*

;----------------------------------------------------------------------------

;
;	S	is set if I-Register is negative, reset otherwise
;	Z	is set if I-Register is zero, reset otherwise
;	H	is reset
;	P/V	contains contents of IFF2
;	N	is reset
;	C	is not affected
;
z80cpu_LD_A_I:
	ext	0x19		; 	xld.ub %r0, [%r4+0x19]		; %A = I
	ld.ub	%r0,[%r4]
	;
	and	%r1,0x8		; 	xand   %r1, %r1, 0x08		; %F = F(00C000)
	swap   %r12, %r0			; %t0[31:24] = A
	or     %r12, %r12			; test A
	ld.w   %r12, %psr		; %t0 = F
	and	%r12,0x3	; 	xand   %r12, %r12, 0x3		; %t0 = F(0000ZS)
	ext	0x1c		; 	xbtst [%r4+0x1c], 0x0		; test IFF2
	btst	[%r4],0x0
	jreq.d 3
	or     %r1, %r12			; %F = F(00C0ZS) *delay*
	or     %r1, 0x04			; %F = F(00CPZS) (skip?)
	;
	ret.d
	sub %r3, 9	; *delay*

;
;	S	is set if R-Register is negative, reset otherwise
;	Z	is set if R-Register is zero, reset otherwise
;	H	is reset
;	P/V	contains contents of IFF2
;	N	is reset
;	C	is not affected
;
z80cpu_LD_A_R:
	ext	0x18		; 	xld.ub %r0, [%r4+0x18]		; %A = R
	ld.ub	%r0,[%r4]
	;
	and	%r1,0x8		; 	xand   %r1, %r1, 0x08		; %F = F(00C000)
	swap   %r12, %r0			; %t0[31:24] = A
	or     %r12, %r12			; test A
	ld.w   %r12, %psr		; %t0 = F
	and	%r12,0x3	; 	xand   %r12, %r12, 0x3		; %t0 = F(0000ZS)
	ext	0x1c		; 	xbtst [%r4+0x1c], 0x0		; test IFF2
	btst	[%r4],0x0
	jreq.d 3
	or     %r1, %r12			; %F = F(00C0ZS) *delay*
	or     %r1, 0x04			; %F = F(00CPZS) (skip?)
	;
	ext	0x80		; 	xand   %r12, %r0 , 0x80		; %t0 = R[7]
	and	%r12,%r0
	ext	0x1		; 	xadd   %r13, %r0 , 1		; %t1 = R+1
	add	%r13,%r0
	ext	0x1		; 	xand   %r13, %r13, 0x7f		; %t1 = R+1[6:0]
	and	%r13,0x3f
	or     %r12, %r13			; %t0 = R[7]|R+1[6:0]
	ext	0x18		; 	xld.b [%r4+0x18], %r12		; R = R[7]|R+1[6:0]
	ld.b	[%r4],%r12
	;
	ret.d
	sub %r3, 9	; *delay*

z80cpu_LD_I_A:
	ext	0x19		; 	xld.b [%r4+0x19], %r0		; I = A
	ld.b	[%r4],%r0
	ret.d
	sub %r3, 9	; *delay*

z80cpu_LD_R_A:
	ext	0x18		; 	xld.b [%r4+0x18], %r0		; R = A
	ld.b	[%r4],%r0
	ret.d
	sub %r3, 9	; *delay*

;****************************************************************************
;	16-Bit Load Group
;****************************************************************************

	.global z80cpu_LD_SP_HL
	.global z80cpu_LD_SP_IX
	.global z80cpu_LD_SP_IY

	.global z80cpu_LD_BC_lm
	.global z80cpu_LD_DE_lm
	.global z80cpu_LD_HL_lm
	.global z80cpu_LD_SP_lm
	.global z80cpu_LD_IX_lm
	.global z80cpu_LD_IY_lm

	.global z80cpu_LD_BC_IlmI
	.global z80cpu_LD_DE_IlmI
	.global z80cpu_LD_HL_IlmI
	.global z80cpu_LD_SP_IlmI
	.global z80cpu_LD_IX_IlmI
	.global z80cpu_LD_IY_IlmI

	.global z80cpu_LD_IlmI_BC
	.global z80cpu_LD_IlmI_DE
	.global z80cpu_LD_IlmI_HL
	.global z80cpu_LD_IlmI_SP
	.global z80cpu_LD_IlmI_IX
	.global z80cpu_LD_IlmI_IY

	.global z80cpu_POP_AF
	.global z80cpu_POP_BC
	.global z80cpu_POP_DE
	.global z80cpu_POP_HL
	.global z80cpu_POP_IX
	.global z80cpu_POP_IY

	.global z80cpu_PUSH_AF
	.global z80cpu_PUSH_BC
	.global z80cpu_PUSH_DE
	.global z80cpu_PUSH_HL
	.global z80cpu_PUSH_IX
	.global z80cpu_PUSH_IY

;----------------------------------------------------------------------------

;#macro LD_SP_rr $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	xld.h [%CPU+SP], %t0		; SP = rr
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_SP_HL:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = rr	; 	LD_SP_rr CYCLE_LD_SP_HL, HL
	ld.uh	%r12,[%r4]
	ext	0x14		; 	xld.h [%r4+0x14], %r12		; SP = rr
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 6			; *delay*
z80cpu_LD_SP_IX:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	LD_SP_rr CYCLE_LD_SP_IX, IX
	ld.uh	%r12,[%r4]
	ext	0x14		; 	xld.h [%r4+0x14], %r12		; SP = rr
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 10			; *delay*
z80cpu_LD_SP_IY:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	LD_SP_rr CYCLE_LD_SP_IY, IY
	ld.uh	%r12,[%r4]
	ext	0x14		; 	xld.h [%r4+0x14], %r12		; SP = rr
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 10			; *delay*

;----------------------------------------------------------------------------

;#macro LD_rr_lm $1, $2
;	ld.ub  %t0, [%PC]+		; %t0 = m
;	ld.ub  %t1, [%PC]+		; %t1 = l
;	xsll   %t1, 8			; %t0 = lm
;	or     %t0, %t1
;	xld.h [%CPU+$2], %t0		; rr = lm
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_BC_lm:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_rr_lm CYCLE_LD_BC_lm, BC
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	ext	0x2		; 	xld.h [%r4+0x2], %r12		; rr = lm
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 10			; *delay*
z80cpu_LD_DE_lm:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_rr_lm CYCLE_LD_DE_lm, DE
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	ext	0x4		; 	xld.h [%r4+0x4], %r12		; rr = lm
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 10			; *delay*
z80cpu_LD_HL_lm:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_rr_lm CYCLE_LD_HL_lm, HL
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	ext	0x6		; 	xld.h [%r4+0x6], %r12		; rr = lm
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 10			; *delay*
z80cpu_LD_SP_lm:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_rr_lm CYCLE_LD_SP_lm, SP
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	ext	0x14		; 	xld.h [%r4+0x14], %r12		; rr = lm
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 10			; *delay*
z80cpu_LD_IX_lm:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_rr_lm CYCLE_LD_IX_lm, IX
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	ext	0x10		; 	xld.h [%r4+0x10], %r12		; rr = lm
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 14			; *delay*
z80cpu_LD_IY_lm:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_rr_lm CYCLE_LD_IY_lm, IY
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	ext	0x12		; 	xld.h [%r4+0x12], %r12		; rr = lm
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 14			; *delay*

;----------------------------------------------------------------------------

;#macro LD_rr_IlmI $1, $2
;	ld.ub  %t0, [%PC]+		; %t0 = m
;	ld.ub  %t1, [%PC]+		; %t1 = l
;	xsll   %t1, 8			; %t0 = lm
;	or     %t0, %t1
;	add    %t0, %MEM		; %t0 = mem+lm
;	ld.ub  %t1, [%t0]+		; %t1 = [mem+lm+0]
;	ld.ub  %t2, [%t0]		; %t2 = [mem+lm+1]
;	xsll   %t2, 8			; %t1 = [mem+lm+0]|[mem+lm+1]<<8
;	or     %t1, %t2
;	xld.h [%CPU+$2], %t1		; rr = [mem+lm+0]|[mem+lm+1]<<8
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_BC_IlmI:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_rr_IlmI CYCLE_LD_BC_IlmI, BC
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	add    %r12, %r5		; %t0 = mem+lm
	ld.ub  %r13, [%r12]+		; %t1 = [mem+lm+0]
	ld.ub  %r14, [%r12]		; %t2 = [mem+lm+1]
	sll	%r14,0x8	; 	xsll   %r14, 8			; %t1 = [mem+lm+0]|[mem+lm+1]<<8
	or     %r13, %r14
	ext	0x2		; 	xld.h [%r4+0x2], %r13		; rr = [mem+lm+0]|[mem+lm+1]<<8
	ld.h	[%r4],%r13
	ret.d
	sub %r3, 20			; *delay*
z80cpu_LD_DE_IlmI:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_rr_IlmI CYCLE_LD_DE_IlmI, DE
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	add    %r12, %r5		; %t0 = mem+lm
	ld.ub  %r13, [%r12]+		; %t1 = [mem+lm+0]
	ld.ub  %r14, [%r12]		; %t2 = [mem+lm+1]
	sll	%r14,0x8	; 	xsll   %r14, 8			; %t1 = [mem+lm+0]|[mem+lm+1]<<8
	or     %r13, %r14
	ext	0x4		; 	xld.h [%r4+0x4], %r13		; rr = [mem+lm+0]|[mem+lm+1]<<8
	ld.h	[%r4],%r13
	ret.d
	sub %r3, 20			; *delay*
z80cpu_LD_HL_IlmI:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_rr_IlmI CYCLE_LD_HL_IlmI, HL
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	add    %r12, %r5		; %t0 = mem+lm
	ld.ub  %r13, [%r12]+		; %t1 = [mem+lm+0]
	ld.ub  %r14, [%r12]		; %t2 = [mem+lm+1]
	sll	%r14,0x8	; 	xsll   %r14, 8			; %t1 = [mem+lm+0]|[mem+lm+1]<<8
	or     %r13, %r14
	ext	0x6		; 	xld.h [%r4+0x6], %r13		; rr = [mem+lm+0]|[mem+lm+1]<<8
	ld.h	[%r4],%r13
	ret.d
	sub %r3, 16			; *delay*
z80cpu_LD_SP_IlmI:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_rr_IlmI CYCLE_LD_SP_IlmI, SP
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	add    %r12, %r5		; %t0 = mem+lm
	ld.ub  %r13, [%r12]+		; %t1 = [mem+lm+0]
	ld.ub  %r14, [%r12]		; %t2 = [mem+lm+1]
	sll	%r14,0x8	; 	xsll   %r14, 8			; %t1 = [mem+lm+0]|[mem+lm+1]<<8
	or     %r13, %r14
	ext	0x14		; 	xld.h [%r4+0x14], %r13		; rr = [mem+lm+0]|[mem+lm+1]<<8
	ld.h	[%r4],%r13
	ret.d
	sub %r3, 20			; *delay*
z80cpu_LD_IX_IlmI:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_rr_IlmI CYCLE_LD_IX_IlmI, IX
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	add    %r12, %r5		; %t0 = mem+lm
	ld.ub  %r13, [%r12]+		; %t1 = [mem+lm+0]
	ld.ub  %r14, [%r12]		; %t2 = [mem+lm+1]
	sll	%r14,0x8	; 	xsll   %r14, 8			; %t1 = [mem+lm+0]|[mem+lm+1]<<8
	or     %r13, %r14
	ext	0x10		; 	xld.h [%r4+0x10], %r13		; rr = [mem+lm+0]|[mem+lm+1]<<8
	ld.h	[%r4],%r13
	ret.d
	sub %r3, 20			; *delay*
z80cpu_LD_IY_IlmI:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_rr_IlmI CYCLE_LD_IY_IlmI, IY
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	add    %r12, %r5		; %t0 = mem+lm
	ld.ub  %r13, [%r12]+		; %t1 = [mem+lm+0]
	ld.ub  %r14, [%r12]		; %t2 = [mem+lm+1]
	sll	%r14,0x8	; 	xsll   %r14, 8			; %t1 = [mem+lm+0]|[mem+lm+1]<<8
	or     %r13, %r14
	ext	0x12		; 	xld.h [%r4+0x12], %r13		; rr = [mem+lm+0]|[mem+lm+1]<<8
	ld.h	[%r4],%r13
	ret.d
	sub %r3, 20			; *delay*

;----------------------------------------------------------------------------

;#macro LD_IlmI_rr $1, $2
;	ld.ub  %t0, [%PC]+		; %t0 = m
;	ld.ub  %t1, [%PC]+		; %t1 = l
;	xsll   %t1, 8			; %t0 = lm
;	or     %t0, %t1
;	add    %t0, %MEM		; %t0 = mem+lm
;	xld.uh %t1, [%CPU+$2]		; %t1 = rr
;	ld.b  [%t0]+, %t1		; [mem+lm+0] = lo(lm)
;	xsrl   %t1, 8			; [mem+lm+1] = hi(lm)
;	ld.b  [%t0], %t1
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_LD_IlmI_BC:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_IlmI_rr CYCLE_LD_IlmI_BC, BC
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	add    %r12, %r5		; %t0 = mem+lm
	ext	0x2		; 	xld.uh %r13, [%r4+0x2]		; %t1 = rr
	ld.uh	%r13,[%r4]
	ld.b  [%r12]+, %r13		; [mem+lm+0] = lo(lm)
	srl	%r13,0x8	; 	xsrl   %r13, 8			; [mem+lm+1] = hi(lm)
	ld.b  [%r12], %r13
	ret.d
	sub %r3, 20			; *delay*
z80cpu_LD_IlmI_DE:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_IlmI_rr CYCLE_LD_IlmI_DE, DE
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	add    %r12, %r5		; %t0 = mem+lm
	ext	0x4		; 	xld.uh %r13, [%r4+0x4]		; %t1 = rr
	ld.uh	%r13,[%r4]
	ld.b  [%r12]+, %r13		; [mem+lm+0] = lo(lm)
	srl	%r13,0x8	; 	xsrl   %r13, 8			; [mem+lm+1] = hi(lm)
	ld.b  [%r12], %r13
	ret.d
	sub %r3, 20			; *delay*
z80cpu_LD_IlmI_HL:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_IlmI_rr CYCLE_LD_IlmI_HL, HL
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	add    %r12, %r5		; %t0 = mem+lm
	ext	0x6		; 	xld.uh %r13, [%r4+0x6]		; %t1 = rr
	ld.uh	%r13,[%r4]
	ld.b  [%r12]+, %r13		; [mem+lm+0] = lo(lm)
	srl	%r13,0x8	; 	xsrl   %r13, 8			; [mem+lm+1] = hi(lm)
	ld.b  [%r12], %r13
	ret.d
	sub %r3, 16			; *delay*
z80cpu_LD_IlmI_SP:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_IlmI_rr CYCLE_LD_IlmI_SP, SP
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	add    %r12, %r5		; %t0 = mem+lm
	ext	0x14		; 	xld.uh %r13, [%r4+0x14]		; %t1 = rr
	ld.uh	%r13,[%r4]
	ld.b  [%r12]+, %r13		; [mem+lm+0] = lo(lm)
	srl	%r13,0x8	; 	xsrl   %r13, 8			; [mem+lm+1] = hi(lm)
	ld.b  [%r12], %r13
	ret.d
	sub %r3, 20			; *delay*
z80cpu_LD_IlmI_IX:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_IlmI_rr CYCLE_LD_IlmI_IX, IX
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	add    %r12, %r5		; %t0 = mem+lm
	ext	0x10		; 	xld.uh %r13, [%r4+0x10]		; %t1 = rr
	ld.uh	%r13,[%r4]
	ld.b  [%r12]+, %r13		; [mem+lm+0] = lo(lm)
	srl	%r13,0x8	; 	xsrl   %r13, 8			; [mem+lm+1] = hi(lm)
	ld.b  [%r12], %r13
	ret.d
	sub %r3, 20			; *delay*
z80cpu_LD_IlmI_IY:
	ld.ub  %r12, [%r2]+		; %t0 = m	; 	LD_IlmI_rr CYCLE_LD_IlmI_IY, IY
	ld.ub  %r13, [%r2]+		; %t1 = l
	sll	%r13,0x8	; 	xsll   %r13, 8			; %t0 = lm
	or     %r12, %r13
	add    %r12, %r5		; %t0 = mem+lm
	ext	0x12		; 	xld.uh %r13, [%r4+0x12]		; %t1 = rr
	ld.uh	%r13,[%r4]
	ld.b  [%r12]+, %r13		; [mem+lm+0] = lo(lm)
	srl	%r13,0x8	; 	xsrl   %r13, 8			; [mem+lm+1] = hi(lm)
	ld.b  [%r12], %r13
	ret.d
	sub %r3, 20			; *delay*

;----------------------------------------------------------------------------

z80cpu_POP_AF:
	ext	z80cpu_pop@rm	; 	xcall z80cpu_pop		; %a0 = AF
	call	z80cpu_pop@rl
	ld.ub %r1, %r10			; %F = F(Z80)
	ext z80cpu_f2psr@ah		; %F = F(C33)
	ext z80cpu_f2psr@al
	ld.ub %r1, [%r1]
	srl	%r10,0x8	; 	xsrl  %r10, 8			; %A = A
	ld.w  %r0, %r10
	ret.d
	sub %r3, 10	; *delay*

;#macro POP_rr $1, $2
;	xcall z80cpu_pop		; %a0 = rr
;	xld.h [%CPU+$2], %a0		; rr = rr
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_POP_BC:
	ext	z80cpu_pop@rm	; 	xcall z80cpu_pop		; %a0 = rr	; 	POP_rr CYCLE_POP_BC, BC
	call	z80cpu_pop@rl
	ext	0x2		; 	xld.h [%r4+0x2], %r10		; rr = rr
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 10			; *delay*
z80cpu_POP_DE:
	ext	z80cpu_pop@rm	; 	xcall z80cpu_pop		; %a0 = rr	; 	POP_rr CYCLE_POP_DE, DE
	call	z80cpu_pop@rl
	ext	0x4		; 	xld.h [%r4+0x4], %r10		; rr = rr
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 10			; *delay*
z80cpu_POP_HL:
	ext	z80cpu_pop@rm	; 	xcall z80cpu_pop		; %a0 = rr	; 	POP_rr CYCLE_POP_HL, HL
	call	z80cpu_pop@rl
	ext	0x6		; 	xld.h [%r4+0x6], %r10		; rr = rr
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 10			; *delay*
z80cpu_POP_IX:
	ext	z80cpu_pop@rm	; 	xcall z80cpu_pop		; %a0 = rr	; 	POP_rr CYCLE_POP_IX, IX
	call	z80cpu_pop@rl
	ext	0x10		; 	xld.h [%r4+0x10], %r10		; rr = rr
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 14			; *delay*
z80cpu_POP_IY:
	ext	z80cpu_pop@rm	; 	xcall z80cpu_pop		; %a0 = rr	; 	POP_rr CYCLE_POP_IY, IY
	call	z80cpu_pop@rl
	ext	0x12		; 	xld.h [%r4+0x12], %r10		; rr = rr
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 14			; *delay*

;----------------------------------------------------------------------------

z80cpu_PUSH_AF:
	ext z80cpu_psr2f@ah		; %a0 = F(Z80)
	ext z80cpu_psr2f@al
	ld.ub %r10, [%r1]
	ld.w  %r12, %r0			; %t0 = A
	sll	%r12,0x8	; 	xsll  %r12, 8			; %a0 = AF
	ext	z80cpu_push@rm	; 	xcall.d z80cpu_push		; push AF
	call.d	z80cpu_push@rl
	or    %r10, %r12			; *delay*
	ret.d
	sub %r3, 11	; *delay*

;#macro PUSH_rr $1, $2
;	xld.uh %a0, [%CPU+$2]		; %a0 = rr
;	xcall z80cpu_push		; push rr
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_PUSH_BC:
	ext	0x2		; 	xld.uh %r10, [%r4+0x2]		; %a0 = rr	; 	PUSH_rr CYCLE_PUSH_BC, BC
	ld.uh	%r10,[%r4]
	ext	z80cpu_push@rm	; 	xcall z80cpu_push		; push rr
	call	z80cpu_push@rl
	ret.d
	sub %r3, 11			; *delay*
z80cpu_PUSH_DE:
	ext	0x4		; 	xld.uh %r10, [%r4+0x4]		; %a0 = rr	; 	PUSH_rr CYCLE_PUSH_DE, DE
	ld.uh	%r10,[%r4]
	ext	z80cpu_push@rm	; 	xcall z80cpu_push		; push rr
	call	z80cpu_push@rl
	ret.d
	sub %r3, 11			; *delay*
z80cpu_PUSH_HL:
	ext	0x6		; 	xld.uh %r10, [%r4+0x6]		; %a0 = rr	; 	PUSH_rr CYCLE_PUSH_HL, HL
	ld.uh	%r10,[%r4]
	ext	z80cpu_push@rm	; 	xcall z80cpu_push		; push rr
	call	z80cpu_push@rl
	ret.d
	sub %r3, 11			; *delay*
z80cpu_PUSH_IX:
	ext	0x10		; 	xld.uh %r10, [%r4+0x10]		; %a0 = rr	; 	PUSH_rr CYCLE_PUSH_IX, IX
	ld.uh	%r10,[%r4]
	ext	z80cpu_push@rm	; 	xcall z80cpu_push		; push rr
	call	z80cpu_push@rl
	ret.d
	sub %r3, 15			; *delay*
z80cpu_PUSH_IY:
	ext	0x12		; 	xld.uh %r10, [%r4+0x12]		; %a0 = rr	; 	PUSH_rr CYCLE_PUSH_IY, IY
	ld.uh	%r10,[%r4]
	ext	z80cpu_push@rm	; 	xcall z80cpu_push		; push rr
	call	z80cpu_push@rl
	ret.d
	sub %r3, 15			; *delay*

;****************************************************************************
;	Exchange, Block Transfer, and Search Group
;****************************************************************************

	.global z80cpu_EX_ISPI_HL
	.global z80cpu_EX_ISPI_IX
	.global z80cpu_EX_ISPI_IY
	.global z80cpu_EX_AF_AF2
	.global z80cpu_EX_DE_HL
	.global z80cpu_EXX

	.global z80cpu_LDI
	.global z80cpu_LDIR
	.global z80cpu_LDD
	.global z80cpu_LDDR

	.global z80cpu_CPI
	.global z80cpu_CPIR
	.global z80cpu_CPD
	.global z80cpu_CPDR

;----------------------------------------------------------------------------

;#macro EX_ISPI_rr $1, $2
;	xld.uh %t0, [%CPU+SP]		; %t0 = SP
;	add    %t0, %MEM		; %t0 = mem+SP+0
;	xld.ub %t1, [%CPU+$2+0]		; %t1 = lo(rr)
;	ld.ub  %t2, [%t0]		; %t2 = [mem+SP+0]
;	ld.b  [%t0]+, %t1		; [mem+SP+0] = lo(rr), %t0 = mem+SP+1
;	xld.b [%CPU+$2+0], %t2		; lo(rr) = [mem+SP+0]
;	xld.ub %t1, [%CPU+$2+1]		; %t1 = hi(rr)
;	ld.ub  %t2, [%t0]		; %t2 = [mem+SP+1]
;	ld.b  [%t0], %t1		; [mem+SP+1] = hi(rr)
;	xld.b [%CPU+$2+1], %t2		; hi(rr) = [mem+SP+1]
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_EX_ISPI_HL:
	ext	0x14		; 	xld.uh %r12, [%r4+0x14]		; %t0 = SP	; 	EX_ISPI_rr CYCLE_EX_ISPI_HL, HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+SP+0
	ext	0x6		; 	xld.ub %r13, [%r4+0x6]		; %t1 = lo(rr)
	ld.ub	%r13,[%r4]
	ld.ub  %r14, [%r12]		; %t2 = [mem+SP+0]
	ld.b  [%r12]+, %r13		; [mem+SP+0] = lo(rr), %t0 = mem+SP+1
	ext	0x6		; 	xld.b [%r4+0x6], %r14		; lo(rr) = [mem+SP+0]
	ld.b	[%r4],%r14
	ext	0x7		; 	xld.ub %r13, [%r4+0x7]		; %t1 = hi(rr)
	ld.ub	%r13,[%r4]
	ld.ub  %r14, [%r12]		; %t2 = [mem+SP+1]
	ld.b  [%r12], %r13		; [mem+SP+1] = hi(rr)
	ext	0x7		; 	xld.b [%r4+0x7], %r14		; hi(rr) = [mem+SP+1]
	ld.b	[%r4],%r14
	ret.d
	sub %r3, 19			; *delay*
z80cpu_EX_ISPI_IX:
	ext	0x14		; 	xld.uh %r12, [%r4+0x14]		; %t0 = SP	; 	EX_ISPI_rr CYCLE_EX_ISPI_IX, IX
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+SP+0
	ext	0x10		; 	xld.ub %r13, [%r4+0x10]		; %t1 = lo(rr)
	ld.ub	%r13,[%r4]
	ld.ub  %r14, [%r12]		; %t2 = [mem+SP+0]
	ld.b  [%r12]+, %r13		; [mem+SP+0] = lo(rr), %t0 = mem+SP+1
	ext	0x10		; 	xld.b [%r4+0x10], %r14		; lo(rr) = [mem+SP+0]
	ld.b	[%r4],%r14
	ext	0x11		; 	xld.ub %r13, [%r4+0x11]		; %t1 = hi(rr)
	ld.ub	%r13,[%r4]
	ld.ub  %r14, [%r12]		; %t2 = [mem+SP+1]
	ld.b  [%r12], %r13		; [mem+SP+1] = hi(rr)
	ext	0x11		; 	xld.b [%r4+0x11], %r14		; hi(rr) = [mem+SP+1]
	ld.b	[%r4],%r14
	ret.d
	sub %r3, 23			; *delay*
z80cpu_EX_ISPI_IY:
	ext	0x14		; 	xld.uh %r12, [%r4+0x14]		; %t0 = SP	; 	EX_ISPI_rr CYCLE_EX_ISPI_IY, IY
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+SP+0
	ext	0x12		; 	xld.ub %r13, [%r4+0x12]		; %t1 = lo(rr)
	ld.ub	%r13,[%r4]
	ld.ub  %r14, [%r12]		; %t2 = [mem+SP+0]
	ld.b  [%r12]+, %r13		; [mem+SP+0] = lo(rr), %t0 = mem+SP+1
	ext	0x12		; 	xld.b [%r4+0x12], %r14		; lo(rr) = [mem+SP+0]
	ld.b	[%r4],%r14
	ext	0x13		; 	xld.ub %r13, [%r4+0x13]		; %t1 = hi(rr)
	ld.ub	%r13,[%r4]
	ld.ub  %r14, [%r12]		; %t2 = [mem+SP+1]
	ld.b  [%r12], %r13		; [mem+SP+1] = hi(rr)
	ext	0x13		; 	xld.b [%r4+0x13], %r14		; hi(rr) = [mem+SP+1]
	ld.b	[%r4],%r14
	ret.d
	sub %r3, 23			; *delay*

z80cpu_EX_AF_AF2:
	ext	0x8		; 	xld.ub %r12, [%r4+0x8]	; %t0 = F'(Z80) ----+
	ld.ub	%r12,[%r4]
	ext	0x9		; 	xld.ub %r13, [%r4+0x9]	; %t1 = A' -------+ |
	ld.ub	%r13,[%r4]
	ext z80cpu_psr2f@ah		; %F = F(Z80) --+ | |
	ext z80cpu_psr2f@al		;               | | |
	ld.ub  %r1, [%r1]			;               | | |
	ext	0x8		; 	xld.b [%r4+0x8], %r1		; F' = F(Z80) <-+ | |
	ld.b	[%r4],%r1
	ext	0x9		; 	xld.b [%r4+0x9], %r0		; A' = A          | |
	ld.b	[%r4],%r0
	ext z80cpu_f2psr@ah		; %F = F'(C33) <--|-+
	ext z80cpu_f2psr@al		;                 |
	ld.ub  %r1, [%r12]		;                 |
	ld.ub  %r0,  %r13			; %A = A' <-------+
	ret.d
	sub %r3, 4	; *delay*

z80cpu_EX_DE_HL:
	ext	0x4		; 	xld.uh %r12, [%r4+0x4]		; %t0 = DE
	ld.uh	%r12,[%r4]
	ext	0x6		; 	xld.uh %r13, [%r4+0x6]		; %t1 = HL
	ld.uh	%r13,[%r4]
	ext	0x6		; 	xld.h [%r4+0x6], %r12		; HL = DE
	ld.h	[%r4],%r12
	ext	0x4		; 	xld.h [%r4+0x4], %r13		; DE = HL
	ld.h	[%r4],%r13
	ret.d
	sub %r3, 4	; *delay*

z80cpu_EXX:
	ext	0x2		; 	xld.uh %r12, [%r4+0x2]		; %t0 = BC
	ld.uh	%r12,[%r4]
	ext	0xa		; 	xld.uh %r13, [%r4+0xa]		; %t1 = BC'
	ld.uh	%r13,[%r4]
	ext	0xa		; 	xld.h [%r4+0xa], %r12		; BC' = BC
	ld.h	[%r4],%r12
	ext	0x2		; 	xld.h [%r4+0x2], %r13		; BC = BC'
	ld.h	[%r4],%r13
	ext	0x4		; 	xld.uh %r12, [%r4+0x4]		; %t0 = DE
	ld.uh	%r12,[%r4]
	ext	0xc		; 	xld.uh %r13, [%r4+0xc]		; %t1 = DE'
	ld.uh	%r13,[%r4]
	ext	0xc		; 	xld.h [%r4+0xc], %r12		; DE' = DE
	ld.h	[%r4],%r12
	ext	0x4		; 	xld.h [%r4+0x4], %r13		; DE = DE'
	ld.h	[%r4],%r13
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	ext	0xe		; 	xld.uh %r13, [%r4+0xe]		; %t1 = HL'
	ld.uh	%r13,[%r4]
	ext	0xe		; 	xld.h [%r4+0xe], %r12		; HL' = HL
	ld.h	[%r4],%r12
	ext	0x6		; 	xld.h [%r4+0x6], %r13		; HL = HL'
	ld.h	[%r4],%r13
	ret.d
	sub %r3, 4		; *delay*

;----------------------------------------------------------------------------

;
;	S	is not affected
;	Z	is not affected
;	H	is reset
;	P/V	is set if BC-1 is not 0, reset otherwise
;	N	is reset
;	C	is not affected
;
z80cpu_LDI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	ext	0x4		; 	xld.uh %r13, [%r4+0x4]		; %t1 = DE
	ld.uh	%r13,[%r4]
	ext	0x2		; 	xld.uh %r14, [%r4+0x2]		; %t2 = BC
	ld.uh	%r14,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	add    %r13, %r5		; %t1 = mem+DE
	ld.b   %r15, [%r12]+		; %t3 = [mem+HL], %t0 = mem+HL+1
	ld.b  [%r13]+, %r15		; [mem+DE] = %t3, %t1 = mem+DE+1
	sub    %r12, %r5		; %t0 = HL+1
	sub    %r13, %r5		; %t1 = DE+1
	sub    %r14, 1			; %t2 = BC-1
	jreq.d 3
	and    %r1, 0xb		; %F = F(00C0ZS) *delay*
	add    %r1, 0x04			; %F = F(00CPZS) (skip?)
	ext	0x6		; 	xld.h [%r4+0x6], %r12		; HL = HL+1
	ld.h	[%r4],%r12
	ext	0x4		; 	xld.h [%r4+0x4], %r13		; DE = DE+1
	ld.h	[%r4],%r13
	ext	0x2		; 	xld.h [%r4+0x2], %r14		; BC = BC-1
	ld.h	[%r4],%r14
	ret.d
	sub %r3, 16		; *delay*

;
;	S	is not affected
;	Z	is not affected
;	H	is reset
;	P/V	is reset
;	N	is reset
;	C	is not affected
;
; [note]
;	* BC-1==0の場合、LDIRの消費サイクル数はLDIと同じです。
;	  従って、LDIRの中でCycleを減らす必要はありません。
;	* BC-1!=0の場合、LDIRの消費サイクル数はLDI+5です。
;	  LDIR命令を繰り返すために、自身の2バイト分戻ります。
;
z80cpu_LDIR:
	call	z80cpu_LDI	; 	xcall z80cpu_LDI		; LDI
	ext	0x4		; 	xand %r9, %r1, 0x04
	and	%r9,%r1
	jreq 3
	sub  %r2, 2			; (skip?)
	sub  %r3, 5			; (skip?)
	ret

;
;	S	is not affected
;	Z	is not affected
;	H	is reset
;	P/V	is set if BC-1 is not 0, reset otherwise
;	N	is reset
;	C	is not affected
;
z80cpu_LDD:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	ext	0x4		; 	xld.uh %r13, [%r4+0x4]		; %t1 = DE
	ld.uh	%r13,[%r4]
	ext	0x2		; 	xld.uh %r14, [%r4+0x2]		; %t2 = BC
	ld.uh	%r14,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	add    %r13, %r5		; %t1 = mem+DE
	ld.b   %r15, [%r12]		; %t3 = [mem+HL]
	sub    %r12, 1			; %t0 = mem+HL-1
	ld.b  [%r13], %r15		; [mem+DE] = %t3
	sub    %r13, 1			; %t1 = mem+DE-1
	sub    %r12, %r5		; %t0 = HL-1
	sub    %r13, %r5		; %t1 = DE-1
	sub    %r14, 1			; %t2 = BC-1
	jreq.d 3
	and    %r1, 0xb		; %F = F(00C0ZS) *delay*
	add    %r1, 0x04			; %F = F(00CPZS) (skip?)
	ext	0x6		; 	xld.h [%r4+0x6], %r12		; HL = HL-1
	ld.h	[%r4],%r12
	ext	0x4		; 	xld.h [%r4+0x4], %r13		; DE = DE-1
	ld.h	[%r4],%r13
	ext	0x2		; 	xld.h [%r4+0x2], %r14		; BC = BC-1
	ld.h	[%r4],%r14
	ret.d
	sub %r3, 16		; *delay*

;
;	S	is not affected
;	Z	is not affected
;	H	is reset
;	P/V	is reset
;	N	is reset
;	C	is not affected
;
; [note]
;	* BC-1==0の場合、LDDRの消費サイクル数はLDDと同じです。
;	  従って、LDDRの中でCycleを減らす必要はありません。
;	* BC-1!=0の場合、LDDRの消費サイクル数はLDD+5です。
;	  LDDR命令を繰り返すために、自身の2バイト分戻ります。
;
z80cpu_LDDR:
	call	z80cpu_LDD	; 	xcall z80cpu_LDD		; LDD
	ext	0x4		; 	xand %r9, %r1, 0x04
	and	%r9,%r1
	jreq 3
	sub  %r2, 2			; (skip?)
	sub  %r3, 5			; (skip?)
	ret

;----------------------------------------------------------------------------

;
;	S	is set if result is negative, reset otherwise
;	Z	is set if A is (HL), reset otherwise
;	H	is set if borrow from bit 4, reset otherwise
;	P/V	is set if BC-1 is not 0, reset otherwise
;	N	is set
;	C	is not affected
;
z80cpu_CPI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r10, [%r12]+		; %a0 = [mem+HL], %t0 = mem+HL+1
	sub    %r12, %r5		; %t0 = HL+1
	ext	0x6		; 	xld.h [%r4+0x6], %r12		; HL  = HL+1
	ld.h	[%r4],%r12
	ext	z80cpu_cp@rm	; 	xcall.d z80cpu_cp		; CP %a0
	call.d	z80cpu_cp@rl
	ld.w   %r6, %r1			; %s0 = F *delay*
	;
	ext	0x2		; 	xld.uh %r12, [%r4+0x2]		; %t0 = BC
	ld.uh	%r12,[%r4]
	and	%r1,0x33	; 	xand   %r1, %r1, -13		; %F  = F(NH00ZS)
	and	%r6,0x8		; 	xand   %r6, %r6, 0x08		; %s0 = F(00C000)
	sub	%r12,0x1	; 	xsub   %r12, %r12, 1		; %t0 = BC-1
	jreq.d 3
	or     %r1, %r6			; %F = F(NHC0ZS) *delay*
	or     %r1, 0x04			; %F = F(NHCPZS) (skip?)
	ext	0x2		; 	xld.h [%r4+0x2], %r12		; BC = BC-1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 16		; *delay*

;
;	S	is set if result is negative, reset otherwise
;	Z	is set if A equals (HL), reset otherwise
;	H	is set if borrow from bit 4, reset otherwise
;	P/V	is set if BC-1 is not 0, reset otherwise
;	N	is set
;	C	is not affected
;
; [note]
;	* BC-1==0の場合、CPIRの消費サイクル数はCPIと同じです。
;	  従って、CPIRの中でCycleを減らす必要はありません。
;	* BC-1!=0の場合、CPIRの消費サイクル数はCPI+5です。
;	  CPIR命令を繰り返すために、自身の2バイト分戻ります。
;
z80cpu_CPIR:
	call	z80cpu_CPI	; 	xcall z80cpu_CPI		; CPI
	ext	0x6		; 	xand %r12, %r1, 0x6
	and	%r12,%r1
	cmp	%r12,0x4	; 	xcmp %r12, 0x04
	jrne 3
	sub  %r2, 2			; (skip?)
	sub  %r3, 5			; (skip?)
	ret

;
;	S	is set if result is negative, reset otherwise
;	Z	is set if A equals (HL), reset otherwise
;	H	is set if borrow from bit 4, reset otherwise
;	P/V	is set if BC-1 is not 0, reset otherwise
;	N	is set
;	C	is not affected
;
z80cpu_CPD:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r10, [%r12]		; %a0 = [mem+HL]
	sub    %r12, 1			; %t0 = mem+HL-1
	sub    %r12, %r5		; %t0 = HL-1
	ext	0x6		; 	xld.h [%r4+0x6], %r12		; HL  = HL-1
	ld.h	[%r4],%r12
	ext	z80cpu_cp@rm	; 	xcall.d z80cpu_cp		; CP %a0
	call.d	z80cpu_cp@rl
	ld.w   %r6, %r1			; %s0 = F *delay*
	;
	ext	0x2		; 	xld.uh %r12, [%r4+0x2]		; %t0 = BC
	ld.uh	%r12,[%r4]
	and	%r1,0x33	; 	xand   %r1, %r1, -13		; %F  = F(NH00ZS)
	and	%r6,0x8		; 	xand   %r6, %r6, 0x08		; %s0 = F(00C000)
	sub	%r12,0x1	; 	xsub   %r12, %r12, 1		; %t0 = BC-1
	jreq.d 3
	or     %r1, %r6			; %F = F(NHC0ZS) *delay*
	or     %r1, 0x04			; %F = F(NHCPZS) (skip?)
	ext	0x2		; 	xld.h [%r4+0x2], %r12		; BC = BC-1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 16		; *delay*

;
;	S	is set if result is negative, reset otherwise
;	Z	is set if A equals (HL), reset otherwise
;	H	is set if borrow from bit 4, reset otherwise
;	P/V	is set if BC-1 is not 0, reset otherwise
;	N	is set
;	C	is not affected
;
; [note]
;	* BC-1==0の場合、CPDRの消費サイクル数はCPDと同じです。
;	  従って、CPDRの中でCycleを減らす必要はありません。
;	* BC-1!=0の場合、CPDRの消費サイクル数はCPD+5です。
;	  CPDR命令を繰り返すために、自身の2バイト分戻ります。
;
z80cpu_CPDR:
	call	z80cpu_CPD	; 	xcall z80cpu_CPD		; CPD
	ext	0x6		; 	xand %r12, %r1, 0x6
	and	%r12,%r1
	cmp	%r12,0x4	; 	xcmp %r12, 0x04
	jrne 3
	sub  %r2, 2			; (skip?)
	sub  %r3, 5			; (skip?)
	ret 

;****************************************************************************
;	8-Bit Arithmetic Group
;****************************************************************************

	.global z80cpu_ADD_A_n
	.global z80cpu_ADD_A_A
	.global z80cpu_ADD_A_B
	.global z80cpu_ADD_A_C
	.global z80cpu_ADD_A_D
	.global z80cpu_ADD_A_E
	.global z80cpu_ADD_A_H
	.global z80cpu_ADD_A_L
	.global z80cpu_ADD_A_IXH
	.global z80cpu_ADD_A_IXL
	.global z80cpu_ADD_A_IYH
	.global z80cpu_ADD_A_IYL
	.global z80cpu_ADD_A_IHLI
	.global z80cpu_ADD_A_IIX_dI
	.global z80cpu_ADD_A_IIY_dI

	.global z80cpu_ADC_A_n
	.global z80cpu_ADC_A_A
	.global z80cpu_ADC_A_B
	.global z80cpu_ADC_A_C
	.global z80cpu_ADC_A_D
	.global z80cpu_ADC_A_E
	.global z80cpu_ADC_A_H
	.global z80cpu_ADC_A_L
	.global z80cpu_ADC_A_IXH
	.global z80cpu_ADC_A_IXL
	.global z80cpu_ADC_A_IYH
	.global z80cpu_ADC_A_IYL
	.global z80cpu_ADC_A_IHLI
	.global z80cpu_ADC_A_IIX_dI
	.global z80cpu_ADC_A_IIY_dI

	.global z80cpu_SUB_n
	.global z80cpu_SUB_A
	.global z80cpu_SUB_B
	.global z80cpu_SUB_C
	.global z80cpu_SUB_D
	.global z80cpu_SUB_E
	.global z80cpu_SUB_H
	.global z80cpu_SUB_L
	.global z80cpu_SUB_IXH
	.global z80cpu_SUB_IXL
	.global z80cpu_SUB_IYH
	.global z80cpu_SUB_IYL
	.global z80cpu_SUB_IHLI
	.global z80cpu_SUB_IIX_dI
	.global z80cpu_SUB_IIY_dI

	.global z80cpu_SBC_A_n
	.global z80cpu_SBC_A_A
	.global z80cpu_SBC_A_B
	.global z80cpu_SBC_A_C
	.global z80cpu_SBC_A_D
	.global z80cpu_SBC_A_E
	.global z80cpu_SBC_A_H
	.global z80cpu_SBC_A_L
	.global z80cpu_SBC_A_IXH
	.global z80cpu_SBC_A_IXL
	.global z80cpu_SBC_A_IYH
	.global z80cpu_SBC_A_IYL
	.global z80cpu_SBC_A_IHLI
	.global z80cpu_SBC_A_IIX_dI
	.global z80cpu_SBC_A_IIY_dI

	.global z80cpu_AND_n
	.global z80cpu_AND_A
	.global z80cpu_AND_B
	.global z80cpu_AND_C
	.global z80cpu_AND_D
	.global z80cpu_AND_E
	.global z80cpu_AND_H
	.global z80cpu_AND_L
	.global z80cpu_AND_IXH
	.global z80cpu_AND_IXL
	.global z80cpu_AND_IYH
	.global z80cpu_AND_IYL
	.global z80cpu_AND_IHLI
	.global z80cpu_AND_IIX_dI
	.global z80cpu_AND_IIY_dI

	.global z80cpu_OR_n
	.global z80cpu_OR_A
	.global z80cpu_OR_B
	.global z80cpu_OR_C
	.global z80cpu_OR_D
	.global z80cpu_OR_E
	.global z80cpu_OR_H
	.global z80cpu_OR_L
	.global z80cpu_OR_IXH
	.global z80cpu_OR_IXL
	.global z80cpu_OR_IYH
	.global z80cpu_OR_IYL
	.global z80cpu_OR_IHLI
	.global z80cpu_OR_IIX_dI
	.global z80cpu_OR_IIY_dI

	.global z80cpu_XOR_n
	.global z80cpu_XOR_A
	.global z80cpu_XOR_B
	.global z80cpu_XOR_C
	.global z80cpu_XOR_D
	.global z80cpu_XOR_E
	.global z80cpu_XOR_H
	.global z80cpu_XOR_L
	.global z80cpu_XOR_IXH
	.global z80cpu_XOR_IXL
	.global z80cpu_XOR_IYH
	.global z80cpu_XOR_IYL
	.global z80cpu_XOR_IHLI
	.global z80cpu_XOR_IIX_dI
	.global z80cpu_XOR_IIY_dI

	.global z80cpu_CP_n
	.global z80cpu_CP_A
	.global z80cpu_CP_B
	.global z80cpu_CP_C
	.global z80cpu_CP_D
	.global z80cpu_CP_E
	.global z80cpu_CP_H
	.global z80cpu_CP_L
	.global z80cpu_CP_IXH
	.global z80cpu_CP_IXL
	.global z80cpu_CP_IYH
	.global z80cpu_CP_IYL
	.global z80cpu_CP_IHLI
	.global z80cpu_CP_IIX_dI
	.global z80cpu_CP_IIY_dI

	.global z80cpu_INC_A
	.global z80cpu_INC_B
	.global z80cpu_INC_C
	.global z80cpu_INC_D
	.global z80cpu_INC_E
	.global z80cpu_INC_H
	.global z80cpu_INC_L
	.global z80cpu_INC_IXH
	.global z80cpu_INC_IXL
	.global z80cpu_INC_IYH
	.global z80cpu_INC_IYL
	.global z80cpu_INC_IHLI
	.global z80cpu_INC_IIX_dI
	.global z80cpu_INC_IIY_dI

	.global z80cpu_DEC_A
	.global z80cpu_DEC_B
	.global z80cpu_DEC_C
	.global z80cpu_DEC_D
	.global z80cpu_DEC_E
	.global z80cpu_DEC_H
	.global z80cpu_DEC_L
	.global z80cpu_DEC_IXH
	.global z80cpu_DEC_IXL
	.global z80cpu_DEC_IYH	
	.global z80cpu_DEC_IYL
	.global z80cpu_DEC_IHLI
	.global z80cpu_DEC_IIX_dI
	.global z80cpu_DEC_IIY_dI

;----------------------------------------------------------------------------

z80cpu_ADD_A_n:
	ld.ub %r10, [%r2]+		; %a0 = n
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 7	; *delay*

z80cpu_ADD_A_A:
	ld.w %r10, %r0			; %a0 = A
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 4	; *delay*

;#macro ADD_A_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xjp.d z80cpu_add8
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_ADD_A_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	ADD_A_r CYCLE_ADD_A_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 4			; *delay*
z80cpu_ADD_A_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	ADD_A_r CYCLE_ADD_A_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 4			; *delay*
z80cpu_ADD_A_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	ADD_A_r CYCLE_ADD_A_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 4			; *delay*
z80cpu_ADD_A_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	ADD_A_r CYCLE_ADD_A_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 4			; *delay*
z80cpu_ADD_A_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	ADD_A_r CYCLE_ADD_A_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 4			; *delay*
z80cpu_ADD_A_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	ADD_A_r CYCLE_ADD_A_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 4			; *delay*
z80cpu_ADD_A_IXH:
	ext	0x11		; 	xld.ub %r10, [%r4+0x11]		; %a0 = r	; 	ADD_A_r CYCLE_ADD_A_IXH, IXH
	ld.ub	%r10,[%r4]
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 8			; *delay*
z80cpu_ADD_A_IXL:
	ext	0x10		; 	xld.ub %r10, [%r4+0x10]		; %a0 = r	; 	ADD_A_r CYCLE_ADD_A_IXL, IXL
	ld.ub	%r10,[%r4]
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 8			; *delay*
z80cpu_ADD_A_IYH:
	ext	0x13		; 	xld.ub %r10, [%r4+0x13]		; %a0 = r	; 	ADD_A_r CYCLE_ADD_A_IYH, IYH
	ld.ub	%r10,[%r4]
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 8			; *delay*
z80cpu_ADD_A_IYL:
	ext	0x12		; 	xld.ub %r10, [%r4+0x12]		; %a0 = r	; 	ADD_A_r CYCLE_ADD_A_IYL, IYL
	ld.ub	%r10,[%r4]
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 8			; *delay*

z80cpu_ADD_A_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r10, [%r12]		; %a0 = [mem+HL]
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 7	; *delay*

;#macro ADD_A_Irr_dI $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	ld.b   %t1, [%PC]+		; %t1 = d (signed)
;	add    %t0, %t1			; %t0 = rr+d
;	add    %t0, %MEM		; %t0 = mem+rr+d
;	ld.ub  %a0, [%t0]		; %a0 = [mem+rr+d]
;	xjp.d z80cpu_add8
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_ADD_A_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	ADD_A_Irr_dI CYCLE_ADD_A_IIX_dI, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 19			; *delay*
z80cpu_ADD_A_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	ADD_A_Irr_dI CYCLE_ADD_A_IIY_dI, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_add8@rm	; 	xjp.d z80cpu_add8
	jp.d	z80cpu_add8@rl
	sub %r3, 19			; *delay*

;----------------------------------------------------------------------------

z80cpu_ADC_A_n:
	ld.ub %r10, [%r2]+		; %a0 = n
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 7	; *delay*

z80cpu_ADC_A_A:
	ld.w %r10, %r0			; %a0 = A
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 4	; *delay*

;#macro ADC_A_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xjp.d z80cpu_adc8
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_ADC_A_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	ADC_A_r CYCLE_ADC_A_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 4			; *delay*
z80cpu_ADC_A_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	ADC_A_r CYCLE_ADC_A_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 4			; *delay*
z80cpu_ADC_A_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	ADC_A_r CYCLE_ADC_A_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 4			; *delay*
z80cpu_ADC_A_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	ADC_A_r CYCLE_ADC_A_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 4			; *delay*
z80cpu_ADC_A_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	ADC_A_r CYCLE_ADC_A_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 4			; *delay*
z80cpu_ADC_A_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	ADC_A_r CYCLE_ADC_A_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 4			; *delay*
z80cpu_ADC_A_IXH:
	ext	0x11		; 	xld.ub %r10, [%r4+0x11]		; %a0 = r	; 	ADC_A_r CYCLE_ADC_A_IXH, IXH
	ld.ub	%r10,[%r4]
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 8			; *delay*
z80cpu_ADC_A_IXL:
	ext	0x10		; 	xld.ub %r10, [%r4+0x10]		; %a0 = r	; 	ADC_A_r CYCLE_ADC_A_IXL, IXL
	ld.ub	%r10,[%r4]
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 8			; *delay*
z80cpu_ADC_A_IYH:
	ext	0x13		; 	xld.ub %r10, [%r4+0x13]		; %a0 = r	; 	ADC_A_r CYCLE_ADC_A_IYH, IYH
	ld.ub	%r10,[%r4]
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 8			; *delay*
z80cpu_ADC_A_IYL:
	ext	0x12		; 	xld.ub %r10, [%r4+0x12]		; %a0 = r	; 	ADC_A_r CYCLE_ADC_A_IYL, IYL
	ld.ub	%r10,[%r4]
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 8			; *delay*

z80cpu_ADC_A_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r10, [%r12]		; %a0 = [mem+HL]
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 7	; *delay*

;#macro ADC_A_Irr_dI $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	ld.b   %t1, [%PC]+		; %t1 = d (signed)
;	add    %t0, %t1			; %t0 = rr+d
;	add    %t0, %MEM		; %t0 = mem+rr+d
;	ld.ub  %a0, [%t0]		; %a0 = [mem+rr+d]
;	xjp.d z80cpu_adc8
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_ADC_A_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	ADC_A_Irr_dI CYCLE_ADC_A_IIX_dI, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 19			; *delay*
z80cpu_ADC_A_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	ADC_A_Irr_dI CYCLE_ADC_A_IIY_dI, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_adc8@rm	; 	xjp.d z80cpu_adc8
	jp.d	z80cpu_adc8@rl
	sub %r3, 19			; *delay*

;----------------------------------------------------------------------------

z80cpu_SUB_n:
	ld.ub %r10, [%r2]+		; %a0 = n
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 7	; *delay*

z80cpu_SUB_A:
	ld.w %r10, %r0			; %a0 = A
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 4	; *delay*

;#macro SUB_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xjp.d z80cpu_sub8
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_SUB_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	SUB_r CYCLE_SUB_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 4			; *delay*
z80cpu_SUB_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	SUB_r CYCLE_SUB_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 4			; *delay*
z80cpu_SUB_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	SUB_r CYCLE_SUB_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 4			; *delay*
z80cpu_SUB_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	SUB_r CYCLE_SUB_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 4			; *delay*
z80cpu_SUB_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	SUB_r CYCLE_SUB_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 4			; *delay*
z80cpu_SUB_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	SUB_r CYCLE_SUB_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 4			; *delay*
z80cpu_SUB_IXH:
	ext	0x11		; 	xld.ub %r10, [%r4+0x11]		; %a0 = r	; 	SUB_r CYCLE_SUB_IXH, IXH
	ld.ub	%r10,[%r4]
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 8			; *delay*
z80cpu_SUB_IXL:
	ext	0x10		; 	xld.ub %r10, [%r4+0x10]		; %a0 = r	; 	SUB_r CYCLE_SUB_IXL, IXL
	ld.ub	%r10,[%r4]
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 8			; *delay*
z80cpu_SUB_IYH:
	ext	0x13		; 	xld.ub %r10, [%r4+0x13]		; %a0 = r	; 	SUB_r CYCLE_SUB_IYH, IYH
	ld.ub	%r10,[%r4]
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 8			; *delay*
z80cpu_SUB_IYL:
	ext	0x12		; 	xld.ub %r10, [%r4+0x12]		; %a0 = r	; 	SUB_r CYCLE_SUB_IYL, IYL
	ld.ub	%r10,[%r4]
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 8			; *delay*

z80cpu_SUB_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r10, [%r12]		; %a0 = [mem+HL]
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 7	; *delay*

;#macro SUB_Irr_dI $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	ld.b   %t1, [%PC]+		; %t1 = d (signed)
;	add    %t0, %t1			; %t0 = rr+d
;	add    %t0, %MEM		; %t0 = mem+rr+d
;	ld.ub  %a0, [%t0]		; %a0 = [mem+rr+d]
;	xjp.d z80cpu_sub8
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_SUB_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	SUB_Irr_dI CYCLE_SUB_IIX_dI, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 19			; *delay*
z80cpu_SUB_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	SUB_Irr_dI CYCLE_SUB_IIY_dI, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_sub8@rm	; 	xjp.d z80cpu_sub8
	jp.d	z80cpu_sub8@rl
	sub %r3, 19			; *delay*

;----------------------------------------------------------------------------

z80cpu_SBC_A_n:
	ld.ub %r10, [%r2]+		; %a0 = n
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 7	; *delay*

z80cpu_SBC_A_A:
	ld.w %r10, %r0			; %a0 = A
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 4	; *delay*

;#macro SBC_A_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xjp.d z80cpu_sbc8
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_SBC_A_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	SBC_A_r CYCLE_SBC_A_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 4			; *delay*
z80cpu_SBC_A_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	SBC_A_r CYCLE_SBC_A_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 4			; *delay*
z80cpu_SBC_A_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	SBC_A_r CYCLE_SBC_A_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 4			; *delay*
z80cpu_SBC_A_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	SBC_A_r CYCLE_SBC_A_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 4			; *delay*
z80cpu_SBC_A_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	SBC_A_r CYCLE_SBC_A_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 4			; *delay*
z80cpu_SBC_A_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	SBC_A_r CYCLE_SBC_A_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 4			; *delay*
z80cpu_SBC_A_IXH:
	ext	0x11		; 	xld.ub %r10, [%r4+0x11]		; %a0 = r	; 	SBC_A_r CYCLE_SBC_A_IXH, IXH
	ld.ub	%r10,[%r4]
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 8			; *delay*
z80cpu_SBC_A_IXL:
	ext	0x10		; 	xld.ub %r10, [%r4+0x10]		; %a0 = r	; 	SBC_A_r CYCLE_SBC_A_IXL, IXL
	ld.ub	%r10,[%r4]
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 8			; *delay*
z80cpu_SBC_A_IYH:
	ext	0x13		; 	xld.ub %r10, [%r4+0x13]		; %a0 = r	; 	SBC_A_r CYCLE_SBC_A_IYH, IYH
	ld.ub	%r10,[%r4]
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 8			; *delay*
z80cpu_SBC_A_IYL:
	ext	0x12		; 	xld.ub %r10, [%r4+0x12]		; %a0 = r	; 	SBC_A_r CYCLE_SBC_A_IYL, IYL
	ld.ub	%r10,[%r4]
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 8			; *delay*

z80cpu_SBC_A_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r10, [%r12]		; %t0 = [mme+HL]
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 7	; *delay*

;#macro SBC_A_Irr_dI $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	ld.b   %t1, [%PC]+		; %t1 = d (signed)
;	add    %t0, %t1			; %t0 = rr+d
;	add    %t0, %MEM		; %t0 = mem+rr+d
;	ld.ub  %a0, [%t0]		; %a0 = [mem+rr+d]
;	xjp.d z80cpu_sbc8
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_SBC_A_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	SBC_A_Irr_dI CYCLE_SBC_A_IIX_dI, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 19			; *delay*
z80cpu_SBC_A_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	SBC_A_Irr_dI CYCLE_SBC_A_IIY_dI, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_sbc8@rm	; 	xjp.d z80cpu_sbc8
	jp.d	z80cpu_sbc8@rl
	sub %r3, 19			; *delay*

;----------------------------------------------------------------------------

z80cpu_AND_n:
	ld.ub %r10, [%r2]+		; %a0 = n
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 7		; *delay*

z80cpu_AND_A:
	ld.w %r10, %r0			; %a0 = A
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 4		; *delay*

;#macro AND_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xjp.d z80cpu_and
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_AND_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	AND_r CYCLE_AND_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 4			; *delay*
z80cpu_AND_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	AND_r CYCLE_AND_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 4			; *delay*
z80cpu_AND_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	AND_r CYCLE_AND_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 4			; *delay*
z80cpu_AND_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	AND_r CYCLE_AND_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 4			; *delay*
z80cpu_AND_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	AND_r CYCLE_AND_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 4			; *delay*
z80cpu_AND_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	AND_r CYCLE_AND_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 4			; *delay*
z80cpu_AND_IXH:
	ext	0x11		; 	xld.ub %r10, [%r4+0x11]		; %a0 = r	; 	AND_r CYCLE_AND_IXH, IXH
	ld.ub	%r10,[%r4]
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 8			; *delay*
z80cpu_AND_IXL:
	ext	0x10		; 	xld.ub %r10, [%r4+0x10]		; %a0 = r	; 	AND_r CYCLE_AND_IXL, IXL
	ld.ub	%r10,[%r4]
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 8			; *delay*
z80cpu_AND_IYH:
	ext	0x13		; 	xld.ub %r10, [%r4+0x13]		; %a0 = r	; 	AND_r CYCLE_AND_IYH, IYH
	ld.ub	%r10,[%r4]
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 8			; *delay*
z80cpu_AND_IYL:
	ext	0x12		; 	xld.ub %r10, [%r4+0x12]		; %a0 = r	; 	AND_r CYCLE_AND_IYL, IYL
	ld.ub	%r10,[%r4]
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 8			; *delay*

z80cpu_AND_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r10, [%r12]		; %a0 = [mem+HL]
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 7	; *delay*

;#macro AND_Irr_dI $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	ld.b   %t1, [%PC]+		; %t1 = d (signed)
;	add    %t0, %t1			; %t0 = rr+d
;	add    %t0, %MEM		; %t0 = mem+rr+d
;	ld.ub  %a0, [%t0]		; %a0 = [mem+rr+d]
;	xjp.d z80cpu_and
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_AND_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	AND_Irr_dI CYCLE_AND_IIX_dI, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 19			; *delay*
z80cpu_AND_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	AND_Irr_dI CYCLE_AND_IIY_dI, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_and@rm	; 	xjp.d z80cpu_and
	jp.d	z80cpu_and@rl
	sub %r3, 19			; *delay*

;----------------------------------------------------------------------------

z80cpu_OR_n:
	ld.ub %r10, [%r2]+		; %a0 = n
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 7		; *delay*

z80cpu_OR_A:
	ld.w %r10, %r0			; %a0 = A
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 4		; *delay*

;#macro OR_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xjp.d z80cpu_or
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_OR_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	OR_r CYCLE_OR_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 4			; *delay*
z80cpu_OR_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	OR_r CYCLE_OR_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 4			; *delay*
z80cpu_OR_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	OR_r CYCLE_OR_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 4			; *delay*
z80cpu_OR_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	OR_r CYCLE_OR_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 4			; *delay*
z80cpu_OR_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	OR_r CYCLE_OR_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 4			; *delay*
z80cpu_OR_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	OR_r CYCLE_OR_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 4			; *delay*
z80cpu_OR_IXH:
	ext	0x11		; 	xld.ub %r10, [%r4+0x11]		; %a0 = r	; 	OR_r CYCLE_OR_IXH, IXH
	ld.ub	%r10,[%r4]
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 8			; *delay*
z80cpu_OR_IXL:
	ext	0x10		; 	xld.ub %r10, [%r4+0x10]		; %a0 = r	; 	OR_r CYCLE_OR_IXL, IXL
	ld.ub	%r10,[%r4]
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 8			; *delay*
z80cpu_OR_IYH:
	ext	0x13		; 	xld.ub %r10, [%r4+0x13]		; %a0 = r	; 	OR_r CYCLE_OR_IYH, IYH
	ld.ub	%r10,[%r4]
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 8			; *delay*
z80cpu_OR_IYL:
	ext	0x12		; 	xld.ub %r10, [%r4+0x12]		; %a0 = r	; 	OR_r CYCLE_OR_IYL, IYL
	ld.ub	%r10,[%r4]
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 8			; *delay*

z80cpu_OR_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r10, [%r12]		; %a0 = [mem+HL]
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 7	; *delay*

;#macro OR_Irr_dI $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	ld.b   %t1, [%PC]+		; %t1 = d (signed)
;	add    %t0, %t1			; %t0 = rr+d
;	add    %t0, %MEM		; %t0 = mem+rr+d
;	ld.ub  %a0, [%t0]		; %a0 = [mem+rr+d]
;	xjp.d z80cpu_or
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_OR_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	OR_Irr_dI CYCLE_OR_IIX_dI, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 19			; *delay*
z80cpu_OR_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	OR_Irr_dI CYCLE_OR_IIY_dI, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_or@rm	; 	xjp.d z80cpu_or
	jp.d	z80cpu_or@rl
	sub %r3, 19			; *delay*

;----------------------------------------------------------------------------

z80cpu_XOR_n:
	ld.ub %r10, [%r2]+		; %a0 = n
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 7		; *delay*

z80cpu_XOR_A:
	ld.w %r10, %r0			; %a0 = A
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 4		; *delay*

;#macro XOR_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xjp.d z80cpu_xor
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_XOR_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	XOR_r CYCLE_XOR_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 4			; *delay*
z80cpu_XOR_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	XOR_r CYCLE_XOR_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 4			; *delay*
z80cpu_XOR_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	XOR_r CYCLE_XOR_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 4			; *delay*
z80cpu_XOR_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	XOR_r CYCLE_XOR_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 4			; *delay*
z80cpu_XOR_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	XOR_r CYCLE_XOR_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 4			; *delay*
z80cpu_XOR_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	XOR_r CYCLE_XOR_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 4			; *delay*
z80cpu_XOR_IXH:
	ext	0x11		; 	xld.ub %r10, [%r4+0x11]		; %a0 = r	; 	XOR_r CYCLE_XOR_IXH, IXH
	ld.ub	%r10,[%r4]
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 8			; *delay*
z80cpu_XOR_IXL:
	ext	0x10		; 	xld.ub %r10, [%r4+0x10]		; %a0 = r	; 	XOR_r CYCLE_XOR_IXL, IXL
	ld.ub	%r10,[%r4]
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 8			; *delay*
z80cpu_XOR_IYH:
	ext	0x13		; 	xld.ub %r10, [%r4+0x13]		; %a0 = r	; 	XOR_r CYCLE_XOR_IYH, IYH
	ld.ub	%r10,[%r4]
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 8			; *delay*
z80cpu_XOR_IYL:
	ext	0x12		; 	xld.ub %r10, [%r4+0x12]		; %a0 = r	; 	XOR_r CYCLE_XOR_IYL, IYL
	ld.ub	%r10,[%r4]
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 8			; *delay*

z80cpu_XOR_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r10, [%r12]		; %t0 = [mem+HL]
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 7	; *delay*

;#macro XOR_Irr_dI $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	ld.b   %t1, [%PC]+		; %t1 = d (signed)
;	add    %t0, %t1			; %t0 = rr+d
;	add    %t0, %MEM		; %t0 = mem+rr+d
;	ld.ub  %a0, [%t0]		; %a0 = [mem+rr+d]
;	xjp.d z80cpu_xor
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_XOR_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	XOR_Irr_dI CYCLE_XOR_IIX_dI, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 19			; *delay*
z80cpu_XOR_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	XOR_Irr_dI CYCLE_XOR_IIY_dI, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_xor@rm	; 	xjp.d z80cpu_xor
	jp.d	z80cpu_xor@rl
	sub %r3, 19			; *delay*

;----------------------------------------------------------------------------

z80cpu_CP_n:
	ld.ub %r10, [%r2]+		; %a0 = n
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 7		; *delay*

z80cpu_CP_A:
	ld.w %r10, %r0			; %a0 = A
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 4		; *delay*

;#macro CP_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xjp.d z80cpu_cp
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_CP_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	CP_r CYCLE_CP_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 4			; *delay*
z80cpu_CP_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	CP_r CYCLE_CP_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 4			; *delay*
z80cpu_CP_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	CP_r CYCLE_CP_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 4			; *delay*
z80cpu_CP_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	CP_r CYCLE_CP_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 4			; *delay*
z80cpu_CP_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	CP_r CYCLE_CP_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 4			; *delay*
z80cpu_CP_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	CP_r CYCLE_CP_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 4			; *delay*
z80cpu_CP_IXH:
	ext	0x11		; 	xld.ub %r10, [%r4+0x11]		; %a0 = r	; 	CP_r CYCLE_CP_IXH, IXH
	ld.ub	%r10,[%r4]
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 8			; *delay*
z80cpu_CP_IXL:
	ext	0x10		; 	xld.ub %r10, [%r4+0x10]		; %a0 = r	; 	CP_r CYCLE_CP_IXL, IXL
	ld.ub	%r10,[%r4]
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 8			; *delay*
z80cpu_CP_IYH:
	ext	0x13		; 	xld.ub %r10, [%r4+0x13]		; %a0 = r	; 	CP_r CYCLE_CP_IYH, IYH
	ld.ub	%r10,[%r4]
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 8			; *delay*
z80cpu_CP_IYL:
	ext	0x12		; 	xld.ub %r10, [%r4+0x12]		; %a0 = r	; 	CP_r CYCLE_CP_IYL, IYL
	ld.ub	%r10,[%r4]
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 8			; *delay*

z80cpu_CP_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	ld.ub  %r10, [%r12]		; %t0 = [mem+HL]
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 7	; *delay*

;#macro CP_Irr_dI $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	ld.b   %t1, [%PC]+		; %t1 = d (signed)
;	add    %t0, %t1			; %t0 = rr+d
;	add    %t0, %MEM		; %t0 = mem+rr+d
;	ld.ub  %a0, [%t0]		; %a0 = [mem+rr+d]
;	xjp.d z80cpu_cp
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_CP_IIX_dI:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	CP_Irr_dI CYCLE_CP_IIX_dI, IX
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 19			; *delay*
z80cpu_CP_IIY_dI:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	CP_Irr_dI CYCLE_CP_IIY_dI, IY
	ld.uh	%r12,[%r4]
	ld.b   %r13, [%r2]+		; %t1 = d (signed)
	add    %r12, %r13			; %t0 = rr+d
	add    %r12, %r5		; %t0 = mem+rr+d
	ld.ub  %r10, [%r12]		; %a0 = [mem+rr+d]
	ext	z80cpu_cp@rm	; 	xjp.d z80cpu_cp
	jp.d	z80cpu_cp@rl
	sub %r3, 19			; *delay*

;----------------------------------------------------------------------------

z80cpu_INC_A:
	ext	z80cpu_inc8@rm	; 	xcall.d z80cpu_inc8
	call.d	z80cpu_inc8@rl
	ld.w %r10, %r0			; %a0 = A *delay*
	ld.w %r0, %r10			; A = A+1
	ret.d
	sub %r3, 4	; *delay*

;#macro INC_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xcall z80cpu_inc8
;	xld.b [%CPU+$2], %a0		; r = r+1
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_INC_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	INC_r CYCLE_INC_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_inc8@rm	; 	xcall z80cpu_inc8
	call	z80cpu_inc8@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 4			; *delay*
z80cpu_INC_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	INC_r CYCLE_INC_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_inc8@rm	; 	xcall z80cpu_inc8
	call	z80cpu_inc8@rl
	ext	0x2		; 	xld.b [%r4+0x2], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 4			; *delay*
z80cpu_INC_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	INC_r CYCLE_INC_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_inc8@rm	; 	xcall z80cpu_inc8
	call	z80cpu_inc8@rl
	ext	0x5		; 	xld.b [%r4+0x5], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 4			; *delay*
z80cpu_INC_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	INC_r CYCLE_INC_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_inc8@rm	; 	xcall z80cpu_inc8
	call	z80cpu_inc8@rl
	ext	0x4		; 	xld.b [%r4+0x4], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 4			; *delay*
z80cpu_INC_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	INC_r CYCLE_INC_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_inc8@rm	; 	xcall z80cpu_inc8
	call	z80cpu_inc8@rl
	ext	0x7		; 	xld.b [%r4+0x7], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 4			; *delay*
z80cpu_INC_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	INC_r CYCLE_INC_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_inc8@rm	; 	xcall z80cpu_inc8
	call	z80cpu_inc8@rl
	ext	0x6		; 	xld.b [%r4+0x6], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 4			; *delay*
z80cpu_INC_IXH:
	ext	0x11		; 	xld.ub %r10, [%r4+0x11]		; %a0 = r	; 	INC_r CYCLE_INC_IXH, IXH
	ld.ub	%r10,[%r4]
	ext	z80cpu_inc8@rm	; 	xcall z80cpu_inc8
	call	z80cpu_inc8@rl
	ext	0x11		; 	xld.b [%r4+0x11], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_INC_IXL:
	ext	0x10		; 	xld.ub %r10, [%r4+0x10]		; %a0 = r	; 	INC_r CYCLE_INC_IXL, IXL
	ld.ub	%r10,[%r4]
	ext	z80cpu_inc8@rm	; 	xcall z80cpu_inc8
	call	z80cpu_inc8@rl
	ext	0x10		; 	xld.b [%r4+0x10], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_INC_IYH:
	ext	0x13		; 	xld.ub %r10, [%r4+0x13]		; %a0 = r	; 	INC_r CYCLE_INC_IYH, IYH
	ld.ub	%r10,[%r4]
	ext	z80cpu_inc8@rm	; 	xcall z80cpu_inc8
	call	z80cpu_inc8@rl
	ext	0x13		; 	xld.b [%r4+0x13], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_INC_IYL:
	ext	0x12		; 	xld.ub %r10, [%r4+0x12]		; %a0 = r	; 	INC_r CYCLE_INC_IYL, IYL
	ld.ub	%r10,[%r4]
	ext	z80cpu_inc8@rm	; 	xcall z80cpu_inc8
	call	z80cpu_inc8@rl
	ext	0x12		; 	xld.b [%r4+0x12], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*

z80cpu_INC_IHLI:
	ext	0x6		; 	xld.uh %r6, [%r4+0x6]		; %s0 = HL
	ld.uh	%r6,[%r4]
	add    %r6, %r5		; %s0 = mem+HL
	ld.ub  %r10, [%r6]		; %a0 = [mem+HL]
	ext	z80cpu_inc8@rm	; 	xcall z80cpu_inc8
	call	z80cpu_inc8@rl
	ld.b  [%r6], %r10		; [mem+HL] = [mem+HL]+1
	ret.d
	sub %r3, 11	; *delay*

;#macro INC_Irr_dI $1, $2
;	xld.uh %s0, [%CPU+$2]		; %s0 = rr
;	ld.b   %t0, [%PC]+		; %t0 = d (signed)
;	add    %s0, %t0			; %s0 = rr+d
;	add    %s0, %MEM		; %s0 = mem+rr+d
;	ld.ub  %a0, [%s0]		; %a0 = [mem+rr+d]
;	xcall z80cpu_inc8
;	ld.b  [%s0], %a0		; [mem+rr+d] = [mem+rr+d]+1
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_INC_IIX_dI:
	ext	0x10		; 	xld.uh %r6, [%r4+0x10]		; %s0 = rr	; 	INC_Irr_dI CYCLE_INC_IIX_dI, IX
	ld.uh	%r6,[%r4]
	ld.b   %r12, [%r2]+		; %t0 = d (signed)
	add    %r6, %r12			; %s0 = rr+d
	add    %r6, %r5		; %s0 = mem+rr+d
	ld.ub  %r10, [%r6]		; %a0 = [mem+rr+d]
	ext	z80cpu_inc8@rm	; 	xcall z80cpu_inc8
	call	z80cpu_inc8@rl
	ld.b  [%r6], %r10		; [mem+rr+d] = [mem+rr+d]+1
	ret.d
	sub %r3, 23			; *delay*
z80cpu_INC_IIY_dI:
	ext	0x12		; 	xld.uh %r6, [%r4+0x12]		; %s0 = rr	; 	INC_Irr_dI CYCLE_INC_IIY_dI, IY
	ld.uh	%r6,[%r4]
	ld.b   %r12, [%r2]+		; %t0 = d (signed)
	add    %r6, %r12			; %s0 = rr+d
	add    %r6, %r5		; %s0 = mem+rr+d
	ld.ub  %r10, [%r6]		; %a0 = [mem+rr+d]
	ext	z80cpu_inc8@rm	; 	xcall z80cpu_inc8
	call	z80cpu_inc8@rl
	ld.b  [%r6], %r10		; [mem+rr+d] = [mem+rr+d]+1
	ret.d
	sub %r3, 23			; *delay*

;----------------------------------------------------------------------------

z80cpu_DEC_A:
	ext	z80cpu_dec8@rm	; 	xcall.d z80cpu_dec8
	call.d	z80cpu_dec8@rl
	ld.w %r10, %r0			; %a0 = A *delay*
	ld.w %r0, %r10			; A = A-1
	ret.d
	sub %r3, 4	; *delay*

;#macro DEC_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xcall z80cpu_dec8
;	xld.b [%CPU+$2], %a0		; r = r+1
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_DEC_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	DEC_r CYCLE_DEC_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8
	call	z80cpu_dec8@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 4			; *delay*
z80cpu_DEC_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	DEC_r CYCLE_DEC_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8
	call	z80cpu_dec8@rl
	ext	0x2		; 	xld.b [%r4+0x2], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 4			; *delay*
z80cpu_DEC_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	DEC_r CYCLE_DEC_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8
	call	z80cpu_dec8@rl
	ext	0x5		; 	xld.b [%r4+0x5], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 4			; *delay*
z80cpu_DEC_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	DEC_r CYCLE_DEC_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8
	call	z80cpu_dec8@rl
	ext	0x4		; 	xld.b [%r4+0x4], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 4			; *delay*
z80cpu_DEC_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	DEC_r CYCLE_DEC_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8
	call	z80cpu_dec8@rl
	ext	0x7		; 	xld.b [%r4+0x7], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 4			; *delay*
z80cpu_DEC_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	DEC_r CYCLE_DEC_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8
	call	z80cpu_dec8@rl
	ext	0x6		; 	xld.b [%r4+0x6], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 4			; *delay*
z80cpu_DEC_IXH:
	ext	0x11		; 	xld.ub %r10, [%r4+0x11]		; %a0 = r	; 	DEC_r CYCLE_DEC_IXH, IXH
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8
	call	z80cpu_dec8@rl
	ext	0x11		; 	xld.b [%r4+0x11], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_DEC_IXL:
	ext	0x10		; 	xld.ub %r10, [%r4+0x10]		; %a0 = r	; 	DEC_r CYCLE_DEC_IXL, IXL
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8
	call	z80cpu_dec8@rl
	ext	0x10		; 	xld.b [%r4+0x10], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_DEC_IYH:
	ext	0x13		; 	xld.ub %r10, [%r4+0x13]		; %a0 = r	; 	DEC_r CYCLE_DEC_IYH, IYH
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8
	call	z80cpu_dec8@rl
	ext	0x13		; 	xld.b [%r4+0x13], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_DEC_IYL:
	ext	0x12		; 	xld.ub %r10, [%r4+0x12]		; %a0 = r	; 	DEC_r CYCLE_DEC_IYL, IYL
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8
	call	z80cpu_dec8@rl
	ext	0x12		; 	xld.b [%r4+0x12], %r10		; r = r+1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*

z80cpu_DEC_IHLI:
	ext	0x6		; 	xld.uh %r6, [%r4+0x6]		; %s0 = HL
	ld.uh	%r6,[%r4]
	add    %r6, %r5		; %s0 = mem+HL
	ld.ub  %r10, [%r6]		; %a0 = [mem+HL]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8
	call	z80cpu_dec8@rl
	ld.b  [%r6], %r10		; [mem+HL] = [mem+HL]-1
	ret.d
	sub %r3, 11	; *delay*

;#macro DEC_Irr_dI $1, $2
;	xld.uh %s0, [%CPU+$2]		; %s0 = rr
;	ld.b   %t0, [%PC]+		; %t0 = d (signed)
;	add    %s0, %t0			; %s0 = rr+d
;	add    %s0, %MEM		; %s0 = mem+rr+d
;	ld.ub  %a0, [%s0]		; %a0 = [mem+rr+d]
;	xcall z80cpu_dec8		
;	ld.b  [%s0], %a0		; [mem+rr+d] = [mem+rr+d]-1
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_DEC_IIX_dI:
	ext	0x10		; 	xld.uh %r6, [%r4+0x10]		; %s0 = rr	; 	DEC_Irr_dI CYCLE_DEC_IIX_dI, IX
	ld.uh	%r6,[%r4]
	ld.b   %r12, [%r2]+		; %t0 = d (signed)
	add    %r6, %r12			; %s0 = rr+d
	add    %r6, %r5		; %s0 = mem+rr+d
	ld.ub  %r10, [%r6]		; %a0 = [mem+rr+d]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8		
	call	z80cpu_dec8@rl
	ld.b  [%r6], %r10		; [mem+rr+d] = [mem+rr+d]-1
	ret.d
	sub %r3, 23			; *delay*
z80cpu_DEC_IIY_dI:
	ext	0x12		; 	xld.uh %r6, [%r4+0x12]		; %s0 = rr	; 	DEC_Irr_dI CYCLE_DEC_IIY_dI, IY
	ld.uh	%r6,[%r4]
	ld.b   %r12, [%r2]+		; %t0 = d (signed)
	add    %r6, %r12			; %s0 = rr+d
	add    %r6, %r5		; %s0 = mem+rr+d
	ld.ub  %r10, [%r6]		; %a0 = [mem+rr+d]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8		
	call	z80cpu_dec8@rl
	ld.b  [%r6], %r10		; [mem+rr+d] = [mem+rr+d]-1
	ret.d
	sub %r3, 23			; *delay*

;****************************************************************************
;	General-Purpose Arithmetic and CPU Control Group
;****************************************************************************

	.global z80cpu_DAA
	.global z80cpu_CPL
	.global z80cpu_NEG
	.global z80cpu_CCF
	.global z80cpu_SCF
	.global z80cpu_NOP
	.global z80cpu_HALT
	.global z80cpu_DI
	.global z80cpu_EI
	.global z80cpu_IM_0
	.global z80cpu_IM_1
	.global z80cpu_IM_2

;----------------------------------------------------------------------------

;
; [note]
;	* 遅くても構わないので、C言語版を呼び出しています。
;	  いずれ、アセンブラ化する予定です。
;
z80cpu_DAA:
	ext	z80cpu_leave@rm	; 	xcall z80cpu_leave		; 実行コンテキストを書き戻します。
	call	z80cpu_leave@rl
	ext	z80cpu_daa@rm	; 	xcall z80cpu_daa
	call	z80cpu_daa@rl
	ext	z80cpu_enter@rm	; 	xjp.d z80cpu_enter		; 実行コンテキストを取り出します。
	jp.d	z80cpu_enter@rl
	sub %r3, 4		; *delay*

;
;	S	is not affected
;	Z	is not affected
;	H	is set
;	P/V	is not affected
;	N	is set
;	C	is not affected
;
z80cpu_CPL:
	not   %r0, %r0			; %A = ~A (signed)
	ld.ub %r0, %r0			; %A = ~A (unsigned)
	ext	0x0		; 	xoor  %r1, %r1, 0x30		; %F = F(NH----) (N,Hが既に1の可能性があるので、xadd不可)
	or	%r1,0x30
	ret.d
	sub %r3, 4		; *delay*

;
;	S	is set if result is negative, reset otherwise
;	Z	is set if result is 0, reset otherwise
;	H	is set if borrow from bit 4, reset otherwise
;	P/V	is set if Accumulator was 80H before operation, reset otherwise
;	N	is set
;	C	is set if Accumulator was not 00H before operation, reset otherwise
;
; [note]
;	* フラグ変化は"SUB 0, A"に等価です。
;	  (推測ですけれど、たぶん間違いないと思います。)
;
z80cpu_NEG:
	ld.w %r10, %r0			; %a0 = A
	ext	z80cpu_sub8@rm	; 	xcall.d z80cpu_sub8
	call.d	z80cpu_sub8@rl
	ld.w %r0, 0			; %A = 0 *delay*
	ret.d
	sub %r3, 8		; *delay*

;
;	S	is not affected
;	Z	is not affected
;	H	previous carry is copied
;	P/V	is not affected
;	N	is reset
;	C	is set if CY was 0 before operation, reset otherwise
;
z80cpu_CCF:
	ext	0x8		; 	xand %r9, %r1, 0x08		; test F(C)
	and	%r9,%r1
	jreq.d 3
	ld.w %r12, 0x08			; if F(C)=0 then %t0 = F(00C000) *delay*
	ld.w %r12, 0x10			; if F(C)=1 then %t0 = F(0H0000) (skip?)
	ext	0x1fff		; 	xand %r1, %r1, -57	; %F = F(000PZS)
	and	%r1,0x7
	or   %r1, %r12			; %F = F(0HCPZS)
	ret.d
	sub %r3, 4		; *delay*

;
;	S	is not affected
;	Z	is not affected
;	H	is reset
;	P/V	is not affected
;	N	is reset
;	C	is set
;
z80cpu_SCF:
	ext	0x1fff		; 	xand %r1, %r1, -49		; %F = F(00-PZS)
	and	%r1,0xf
	or	%r1,0x8		; 	xoor %r1, %r1, 0x08			; %F = F(001PZS) (Cが既に1の可能性があるので、xadd不可)
	ret.d
	sub %r3, 4		; *delay*

z80cpu_NOP:
	;** no job **
	ret.d
	sub %r3, 4		; *delay*

z80cpu_HALT:
	ext	0x1d		; 	xbset [%r4+0x1d], 0x0		; HALT = 1
	bset	[%r4],0x0
	ret.d
	ld.w %r3, 0			; (残りCycleを0にしてrunを抜けます) *delay*

z80cpu_DI:
	ext	0x1b		; 	xbclr [%r4+0x1b], 0x0		; IFF1 = 0
	bclr	[%r4],0x0
	ext	0x1c		; 	xbclr [%r4+0x1c], 0x0		; IFF2 = 0
	bclr	[%r4],0x0
	ret.d
	sub %r3, 4		; *delay*

z80cpu_EI:
	ext	0x1b		; 	xbset [%r4+0x1b], 0x0		; IFF1 = 1
	bset	[%r4],0x0
	ext	0x1c		; 	xbset [%r4+0x1c], 0x0		; IFF2 = 1
	bset	[%r4],0x0
	ret.d
	sub %r3, 4		; *delay*

z80cpu_IM_0:
	ld.w	%r12,0x0	; 	xld.w  %r12, 0			; IM = 0
	ext	0x1a		; 	xld.b [%r4+0x1a], %r12
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8		; *delay*

z80cpu_IM_1:
	ld.w	%r12,0x1	; 	xld.w  %r12, 1			; IM = 1
	ext	0x1a		; 	xld.b [%r4+0x1a], %r12
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8		; *delay*

z80cpu_IM_2:
	ld.w	%r12,0x2	; 	xld.w  %r12, 2			; IM = 2
	ext	0x1a		; 	xld.b [%r4+0x1a], %r12
	ld.b	[%r4],%r12
	ret.d
	sub %r3, 8		; *delay*

;****************************************************************************
;	16-Bit Arithmetic Group
;****************************************************************************

	.global z80cpu_ADD_HL_BC
	.global z80cpu_ADD_HL_DE
	.global z80cpu_ADD_HL_HL
	.global z80cpu_ADD_HL_SP
	.global z80cpu_ADD_IX_BC
	.global z80cpu_ADD_IX_DE
	.global z80cpu_ADD_IX_IX
	.global z80cpu_ADD_IX_SP
	.global z80cpu_ADD_IY_BC
	.global z80cpu_ADD_IY_DE
	.global z80cpu_ADD_IY_IY
	.global z80cpu_ADD_IY_SP

	.global z80cpu_ADC_HL_BC
	.global z80cpu_ADC_HL_DE
	.global z80cpu_ADC_HL_HL
	.global z80cpu_ADC_HL_SP

	.global z80cpu_SBC_HL_BC
	.global z80cpu_SBC_HL_DE
	.global z80cpu_SBC_HL_HL
	.global z80cpu_SBC_HL_SP

	.global z80cpu_INC_BC
	.global z80cpu_INC_DE
	.global z80cpu_INC_HL
	.global z80cpu_INC_SP
	.global z80cpu_INC_IX
	.global z80cpu_INC_IY

	.global z80cpu_DEC_BC
	.global z80cpu_DEC_DE
	.global z80cpu_DEC_HL
	.global z80cpu_DEC_SP
	.global z80cpu_DEC_IX
	.global z80cpu_DEC_IY

;----------------------------------------------------------------------------

;#macro ADD_rr_ss $1, $2, $3
;	xld.uh %a0, [%CPU+$2]		; %a0 = rr
;	xld.uh %a1, [%CPU+$3]		; %a1 = ss
;	xcall z80cpu_add16
;	xld.h [%CPU+$2], %a0		; %rr = rr+ss
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_ADD_HL_BC:
	ext	0x6		; 	xld.uh %r10, [%r4+0x6]		; %a0 = rr	; 	ADD_rr_ss CYCLE_ADD_HL_BC, HL, BC
	ld.uh	%r10,[%r4]
	ext	0x2		; 	xld.uh %r11, [%r4+0x2]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_add16@rm	; 	xcall z80cpu_add16
	call	z80cpu_add16@rl
	ext	0x6		; 	xld.h [%r4+0x6], %r10		; %rr = rr+ss
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 11			; *delay*
z80cpu_ADD_HL_DE:
	ext	0x6		; 	xld.uh %r10, [%r4+0x6]		; %a0 = rr	; 	ADD_rr_ss CYCLE_ADD_HL_DE, HL, DE
	ld.uh	%r10,[%r4]
	ext	0x4		; 	xld.uh %r11, [%r4+0x4]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_add16@rm	; 	xcall z80cpu_add16
	call	z80cpu_add16@rl
	ext	0x6		; 	xld.h [%r4+0x6], %r10		; %rr = rr+ss
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 11			; *delay*
z80cpu_ADD_HL_HL:
	ext	0x6		; 	xld.uh %r10, [%r4+0x6]		; %a0 = rr	; 	ADD_rr_ss CYCLE_ADD_HL_HL, HL, HL
	ld.uh	%r10,[%r4]
	ext	0x6		; 	xld.uh %r11, [%r4+0x6]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_add16@rm	; 	xcall z80cpu_add16
	call	z80cpu_add16@rl
	ext	0x6		; 	xld.h [%r4+0x6], %r10		; %rr = rr+ss
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 11			; *delay*
z80cpu_ADD_HL_SP:
	ext	0x6		; 	xld.uh %r10, [%r4+0x6]		; %a0 = rr	; 	ADD_rr_ss CYCLE_ADD_HL_SP, HL, SP
	ld.uh	%r10,[%r4]
	ext	0x14		; 	xld.uh %r11, [%r4+0x14]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_add16@rm	; 	xcall z80cpu_add16
	call	z80cpu_add16@rl
	ext	0x6		; 	xld.h [%r4+0x6], %r10		; %rr = rr+ss
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 11			; *delay*
z80cpu_ADD_IX_BC:
	ext	0x10		; 	xld.uh %r10, [%r4+0x10]		; %a0 = rr	; 	ADD_rr_ss CYCLE_ADD_IX_BC, IX, BC
	ld.uh	%r10,[%r4]
	ext	0x2		; 	xld.uh %r11, [%r4+0x2]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_add16@rm	; 	xcall z80cpu_add16
	call	z80cpu_add16@rl
	ext	0x10		; 	xld.h [%r4+0x10], %r10		; %rr = rr+ss
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*
z80cpu_ADD_IX_DE:
	ext	0x10		; 	xld.uh %r10, [%r4+0x10]		; %a0 = rr	; 	ADD_rr_ss CYCLE_ADD_IX_DE, IX, DE
	ld.uh	%r10,[%r4]
	ext	0x4		; 	xld.uh %r11, [%r4+0x4]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_add16@rm	; 	xcall z80cpu_add16
	call	z80cpu_add16@rl
	ext	0x10		; 	xld.h [%r4+0x10], %r10		; %rr = rr+ss
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*
z80cpu_ADD_IX_IX:
	ext	0x10		; 	xld.uh %r10, [%r4+0x10]		; %a0 = rr	; 	ADD_rr_ss CYCLE_ADD_IX_IX, IX, IX
	ld.uh	%r10,[%r4]
	ext	0x10		; 	xld.uh %r11, [%r4+0x10]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_add16@rm	; 	xcall z80cpu_add16
	call	z80cpu_add16@rl
	ext	0x10		; 	xld.h [%r4+0x10], %r10		; %rr = rr+ss
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*
z80cpu_ADD_IX_SP:
	ext	0x10		; 	xld.uh %r10, [%r4+0x10]		; %a0 = rr	; 	ADD_rr_ss CYCLE_ADD_IX_SP, IX, SP
	ld.uh	%r10,[%r4]
	ext	0x14		; 	xld.uh %r11, [%r4+0x14]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_add16@rm	; 	xcall z80cpu_add16
	call	z80cpu_add16@rl
	ext	0x10		; 	xld.h [%r4+0x10], %r10		; %rr = rr+ss
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*
z80cpu_ADD_IY_BC:
	ext	0x12		; 	xld.uh %r10, [%r4+0x12]		; %a0 = rr	; 	ADD_rr_ss CYCLE_ADD_IY_BC, IY, BC
	ld.uh	%r10,[%r4]
	ext	0x2		; 	xld.uh %r11, [%r4+0x2]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_add16@rm	; 	xcall z80cpu_add16
	call	z80cpu_add16@rl
	ext	0x12		; 	xld.h [%r4+0x12], %r10		; %rr = rr+ss
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*
z80cpu_ADD_IY_DE:
	ext	0x12		; 	xld.uh %r10, [%r4+0x12]		; %a0 = rr	; 	ADD_rr_ss CYCLE_ADD_IY_DE, IY, DE
	ld.uh	%r10,[%r4]
	ext	0x4		; 	xld.uh %r11, [%r4+0x4]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_add16@rm	; 	xcall z80cpu_add16
	call	z80cpu_add16@rl
	ext	0x12		; 	xld.h [%r4+0x12], %r10		; %rr = rr+ss
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*
z80cpu_ADD_IY_IY:
	ext	0x12		; 	xld.uh %r10, [%r4+0x12]		; %a0 = rr	; 	ADD_rr_ss CYCLE_ADD_IY_IY, IY, IY
	ld.uh	%r10,[%r4]
	ext	0x12		; 	xld.uh %r11, [%r4+0x12]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_add16@rm	; 	xcall z80cpu_add16
	call	z80cpu_add16@rl
	ext	0x12		; 	xld.h [%r4+0x12], %r10		; %rr = rr+ss
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*
z80cpu_ADD_IY_SP:
	ext	0x12		; 	xld.uh %r10, [%r4+0x12]		; %a0 = rr	; 	ADD_rr_ss CYCLE_ADD_IY_SP, IY, SP
	ld.uh	%r10,[%r4]
	ext	0x14		; 	xld.uh %r11, [%r4+0x14]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_add16@rm	; 	xcall z80cpu_add16
	call	z80cpu_add16@rl
	ext	0x12		; 	xld.h [%r4+0x12], %r10		; %rr = rr+ss
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*

;----------------------------------------------------------------------------

;#macro ADC_rr_ss $1, $2, $3
;	xld.uh %a0, [%CPU+$2]		; %a0 = rr
;	xld.uh %a1, [%CPU+$3]		; %a1 = ss
;	xcall z80cpu_adc16
;	xld.h [%CPU+$2], %a0		; rr = rr+ss+F(C)
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_ADC_HL_BC:
	ext	0x6		; 	xld.uh %r10, [%r4+0x6]		; %a0 = rr	; 	ADC_rr_ss CYCLE_ADC_HL_BC, HL, BC
	ld.uh	%r10,[%r4]
	ext	0x2		; 	xld.uh %r11, [%r4+0x2]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_adc16@rm	; 	xcall z80cpu_adc16
	call	z80cpu_adc16@rl
	ext	0x6		; 	xld.h [%r4+0x6], %r10		; rr = rr+ss+F(C)
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*
z80cpu_ADC_HL_DE:
	ext	0x6		; 	xld.uh %r10, [%r4+0x6]		; %a0 = rr	; 	ADC_rr_ss CYCLE_ADC_HL_DE, HL, DE
	ld.uh	%r10,[%r4]
	ext	0x4		; 	xld.uh %r11, [%r4+0x4]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_adc16@rm	; 	xcall z80cpu_adc16
	call	z80cpu_adc16@rl
	ext	0x6		; 	xld.h [%r4+0x6], %r10		; rr = rr+ss+F(C)
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*
z80cpu_ADC_HL_HL:
	ext	0x6		; 	xld.uh %r10, [%r4+0x6]		; %a0 = rr	; 	ADC_rr_ss CYCLE_ADC_HL_HL, HL, HL
	ld.uh	%r10,[%r4]
	ext	0x6		; 	xld.uh %r11, [%r4+0x6]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_adc16@rm	; 	xcall z80cpu_adc16
	call	z80cpu_adc16@rl
	ext	0x6		; 	xld.h [%r4+0x6], %r10		; rr = rr+ss+F(C)
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*
z80cpu_ADC_HL_SP:
	ext	0x6		; 	xld.uh %r10, [%r4+0x6]		; %a0 = rr	; 	ADC_rr_ss CYCLE_ADC_HL_SP, HL, SP
	ld.uh	%r10,[%r4]
	ext	0x14		; 	xld.uh %r11, [%r4+0x14]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_adc16@rm	; 	xcall z80cpu_adc16
	call	z80cpu_adc16@rl
	ext	0x6		; 	xld.h [%r4+0x6], %r10		; rr = rr+ss+F(C)
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*

;----------------------------------------------------------------------------

;#macro SBC_rr_ss $1, $2, $3
;	xld.uh %a0, [%CPU+$2]		; %a0 = rr
;	xld.uh %a1, [%CPU+$3]		; %a1 = ss
;	xcall z80cpu_sbc16
;	xld.h [%CPU+$2], %a0		; rr = rr-ss-F(C)
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_SBC_HL_BC:
	ext	0x6		; 	xld.uh %r10, [%r4+0x6]		; %a0 = rr	; 	SBC_rr_ss CYCLE_SBC_HL_BC, HL, BC
	ld.uh	%r10,[%r4]
	ext	0x2		; 	xld.uh %r11, [%r4+0x2]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_sbc16@rm	; 	xcall z80cpu_sbc16
	call	z80cpu_sbc16@rl
	ext	0x6		; 	xld.h [%r4+0x6], %r10		; rr = rr-ss-F(C)
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*
z80cpu_SBC_HL_DE:
	ext	0x6		; 	xld.uh %r10, [%r4+0x6]		; %a0 = rr	; 	SBC_rr_ss CYCLE_SBC_HL_DE, HL, DE
	ld.uh	%r10,[%r4]
	ext	0x4		; 	xld.uh %r11, [%r4+0x4]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_sbc16@rm	; 	xcall z80cpu_sbc16
	call	z80cpu_sbc16@rl
	ext	0x6		; 	xld.h [%r4+0x6], %r10		; rr = rr-ss-F(C)
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*
z80cpu_SBC_HL_HL:
	ext	0x6		; 	xld.uh %r10, [%r4+0x6]		; %a0 = rr	; 	SBC_rr_ss CYCLE_SBC_HL_HL, HL, HL
	ld.uh	%r10,[%r4]
	ext	0x6		; 	xld.uh %r11, [%r4+0x6]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_sbc16@rm	; 	xcall z80cpu_sbc16
	call	z80cpu_sbc16@rl
	ext	0x6		; 	xld.h [%r4+0x6], %r10		; rr = rr-ss-F(C)
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*
z80cpu_SBC_HL_SP:
	ext	0x6		; 	xld.uh %r10, [%r4+0x6]		; %a0 = rr	; 	SBC_rr_ss CYCLE_SBC_HL_SP, HL, SP
	ld.uh	%r10,[%r4]
	ext	0x14		; 	xld.uh %r11, [%r4+0x14]		; %a1 = ss
	ld.uh	%r11,[%r4]
	ext	z80cpu_sbc16@rm	; 	xcall z80cpu_sbc16
	call	z80cpu_sbc16@rl
	ext	0x6		; 	xld.h [%r4+0x6], %r10		; rr = rr-ss-F(C)
	ld.h	[%r4],%r10
	ret.d
	sub %r3, 15			; *delay*

;----------------------------------------------------------------------------

;
;	Condition Bits Affected: None
;
;#macro INC_rr $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	xadd   %t0, %t0, 1		; %t0 = rr+1
;	xld.h [%CPU+$2], %t0		; rr = rr+1
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_INC_BC:
	ext	0x2		; 	xld.uh %r12, [%r4+0x2]		; %t0 = rr	; 	INC_rr CYCLE_INC_BC, BC
	ld.uh	%r12,[%r4]
	add	%r12,0x1	; 	xadd   %r12, %r12, 1		; %t0 = rr+1
	ext	0x2		; 	xld.h [%r4+0x2], %r12		; rr = rr+1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 6			; *delay*
z80cpu_INC_DE:
	ext	0x4		; 	xld.uh %r12, [%r4+0x4]		; %t0 = rr	; 	INC_rr CYCLE_INC_DE, DE
	ld.uh	%r12,[%r4]
	add	%r12,0x1	; 	xadd   %r12, %r12, 1		; %t0 = rr+1
	ext	0x4		; 	xld.h [%r4+0x4], %r12		; rr = rr+1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 6			; *delay*
z80cpu_INC_HL:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = rr	; 	INC_rr CYCLE_INC_HL, HL
	ld.uh	%r12,[%r4]
	add	%r12,0x1	; 	xadd   %r12, %r12, 1		; %t0 = rr+1
	ext	0x6		; 	xld.h [%r4+0x6], %r12		; rr = rr+1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 6			; *delay*
z80cpu_INC_SP:
	ext	0x14		; 	xld.uh %r12, [%r4+0x14]		; %t0 = rr	; 	INC_rr CYCLE_INC_SP, SP
	ld.uh	%r12,[%r4]
	add	%r12,0x1	; 	xadd   %r12, %r12, 1		; %t0 = rr+1
	ext	0x14		; 	xld.h [%r4+0x14], %r12		; rr = rr+1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 6			; *delay*
z80cpu_INC_IX:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	INC_rr CYCLE_INC_IX, IX
	ld.uh	%r12,[%r4]
	add	%r12,0x1	; 	xadd   %r12, %r12, 1		; %t0 = rr+1
	ext	0x10		; 	xld.h [%r4+0x10], %r12		; rr = rr+1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 10			; *delay*
z80cpu_INC_IY:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	INC_rr CYCLE_INC_IY, IY
	ld.uh	%r12,[%r4]
	add	%r12,0x1	; 	xadd   %r12, %r12, 1		; %t0 = rr+1
	ext	0x12		; 	xld.h [%r4+0x12], %r12		; rr = rr+1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 10			; *delay*

;----------------------------------------------------------------------------

;
;	Condition Bits Affected: None
;
;#macro DEC_rr $1, $2
;	xld.uh %t0, [%CPU+$2]		; %t0 = rr
;	xsub   %t0, %t0, 1		; %t0 = rr-1
;	xld.h [%CPU+$2], %t0		; rr = rr-1
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_DEC_BC:
	ext	0x2		; 	xld.uh %r12, [%r4+0x2]		; %t0 = rr	; 	DEC_rr CYCLE_DEC_BC, BC
	ld.uh	%r12,[%r4]
	sub	%r12,0x1	; 	xsub   %r12, %r12, 1		; %t0 = rr-1
	ext	0x2		; 	xld.h [%r4+0x2], %r12		; rr = rr-1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 6			; *delay*
z80cpu_DEC_DE:
	ext	0x4		; 	xld.uh %r12, [%r4+0x4]		; %t0 = rr	; 	DEC_rr CYCLE_DEC_DE, DE
	ld.uh	%r12,[%r4]
	sub	%r12,0x1	; 	xsub   %r12, %r12, 1		; %t0 = rr-1
	ext	0x4		; 	xld.h [%r4+0x4], %r12		; rr = rr-1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 6			; *delay*
z80cpu_DEC_HL:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = rr	; 	DEC_rr CYCLE_DEC_HL, HL
	ld.uh	%r12,[%r4]
	sub	%r12,0x1	; 	xsub   %r12, %r12, 1		; %t0 = rr-1
	ext	0x6		; 	xld.h [%r4+0x6], %r12		; rr = rr-1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 6			; *delay*
z80cpu_DEC_SP:
	ext	0x14		; 	xld.uh %r12, [%r4+0x14]		; %t0 = rr	; 	DEC_rr CYCLE_DEC_SP, SP
	ld.uh	%r12,[%r4]
	sub	%r12,0x1	; 	xsub   %r12, %r12, 1		; %t0 = rr-1
	ext	0x14		; 	xld.h [%r4+0x14], %r12		; rr = rr-1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 6			; *delay*
z80cpu_DEC_IX:
	ext	0x10		; 	xld.uh %r12, [%r4+0x10]		; %t0 = rr	; 	DEC_rr CYCLE_DEC_IX, IX
	ld.uh	%r12,[%r4]
	sub	%r12,0x1	; 	xsub   %r12, %r12, 1		; %t0 = rr-1
	ext	0x10		; 	xld.h [%r4+0x10], %r12		; rr = rr-1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 10			; *delay*
z80cpu_DEC_IY:
	ext	0x12		; 	xld.uh %r12, [%r4+0x12]		; %t0 = rr	; 	DEC_rr CYCLE_DEC_IY, IY
	ld.uh	%r12,[%r4]
	sub	%r12,0x1	; 	xsub   %r12, %r12, 1		; %t0 = rr-1
	ext	0x12		; 	xld.h [%r4+0x12], %r12		; rr = rr-1
	ld.h	[%r4],%r12
	ret.d
	sub %r3, 10			; *delay*

;****************************************************************************
;	Rotate and Shift Group
;****************************************************************************

	.global z80cpu_RLA
	.global z80cpu_RLCA
	.global z80cpu_RRA
	.global z80cpu_RRCA

	.global z80cpu_RL_A
	.global z80cpu_RL_B
	.global z80cpu_RL_C
	.global z80cpu_RL_D
	.global z80cpu_RL_E
	.global z80cpu_RL_H
	.global z80cpu_RL_L
	.global z80cpu_RL_IHLI
	.global z80cpu_RL_IaddrI

	.global z80cpu_RLC_A
	.global z80cpu_RLC_B
	.global z80cpu_RLC_C
	.global z80cpu_RLC_D
	.global z80cpu_RLC_E
	.global z80cpu_RLC_H
	.global z80cpu_RLC_L
	.global z80cpu_RLC_IHLI
	.global z80cpu_RLC_IaddrI

	.global z80cpu_RR_A
	.global z80cpu_RR_B
	.global z80cpu_RR_C
	.global z80cpu_RR_D
	.global z80cpu_RR_E
	.global z80cpu_RR_H
	.global z80cpu_RR_L
	.global z80cpu_RR_IHLI
	.global z80cpu_RR_IaddrI

	.global z80cpu_RRC_A
	.global z80cpu_RRC_B
	.global z80cpu_RRC_C
	.global z80cpu_RRC_D
	.global z80cpu_RRC_E
	.global z80cpu_RRC_H
	.global z80cpu_RRC_L
	.global z80cpu_RRC_IHLI
	.global z80cpu_RRC_IaddrI

	.global z80cpu_SLA_A
	.global z80cpu_SLA_B
	.global z80cpu_SLA_C
	.global z80cpu_SLA_D
	.global z80cpu_SLA_E
	.global z80cpu_SLA_H
	.global z80cpu_SLA_L
	.global z80cpu_SLA_IHLI
	.global z80cpu_SLA_IaddrI

	.global z80cpu_SRA_A
	.global z80cpu_SRA_B
	.global z80cpu_SRA_C
	.global z80cpu_SRA_D
	.global z80cpu_SRA_E
	.global z80cpu_SRA_H
	.global z80cpu_SRA_L
	.global z80cpu_SRA_IHLI
	.global z80cpu_SRA_IaddrI

	.global z80cpu_SRL_A
	.global z80cpu_SRL_B
	.global z80cpu_SRL_C
	.global z80cpu_SRL_D
	.global z80cpu_SRL_E
	.global z80cpu_SRL_H
	.global z80cpu_SRL_L
	.global z80cpu_SRL_IHLI
	.global z80cpu_SRL_IaddrI

	.global z80cpu_RLD
	.global z80cpu_RRD

;----------------------------------------------------------------------------

;
;	S	is not affected
;	Z	is not affected
;	H	is reset
;	P/V	is not affected
;	N	is reset
;	C	is data from bit 7 of Accumulator
;
; [note]
;	* "RL A"とはフラグ変化が異なることに注意してください。
;
z80cpu_RLA:
	ld.w  %r12, %r0			; %t0 = 0:AAAAAAAA
	sll	%r0,0x1		; 	xsll  %r0, 1			; %A  = A:AAAAAAA0
	ext	0x8		; 	xand  %r13, %r1, 0x08		; %t1 = 0:0000C000
	and	%r13,%r1
	srl	%r13,0x3	; 	xsrl  %r13, 0x3			; %t1 = 0:0000000C
	or    %r0, %r13			; %A  = A:AAAAAAAC
	ld.ub %r0, %r0			; %A  = 0:AAAAAAAC
	;
	and	%r1,0x7		; 	xand  %r1, %r1, 0x7		; F   = F(00000PZS)
	srl	%r12,0x4	; 	xsrl  %r12, 0x4			; %t0 =   0000AAAA
	and	%r12,0x8	; 	xand  %r12, %r12, 0x08		; %t0 =   0000A000
	or    %r1, %r12			; %F  = F(0000CPZS)
	ret.d
	sub %r3, 4		; *delay*

;
;	S	is not affected
;	Z	is not affected
;	H	is reset
;	P/V	is not affected
;	N	is reset
;	C	is data from bit 7 of Accumulator
;
; [note]
;	* "RLC A"とはフラグ変化が異なることに注意してください。
;
z80cpu_RLCA:
	ld.w  %r12, %r0			; %t0 = 0:AAAAAAAA
	ld.w  %r13, %r0			; %t1 = 0:AAAAAAAA
	sll	%r0,0x1		; 	xsll  %r0, 1			; %A  = A:AAAAAAA0
	srl	%r13,0x7	; 	xsrl  %r13, 7			; %t1 = 0:0000000A
	or    %r0, %r13			; %A  = A:AAAAAAAA
	ld.ub %r0, %r0			; %A  = 0:AAAAAAAA
	;
	and	%r1,0x7		; 	xand  %r1, %r1, 0x7		; F   = F(00000PZS)
	srl	%r12,0x4	; 	xsrl  %r12, 0x4			; %t0 =   0000AAAA
	and	%r12,0x8	; 	xand  %r12, %r12, 0x08		; %t0 =   0000A000
	or    %r1, %r12			; %F  = F(0000CPZS)
	ret.d
	sub %r3, 4		; *delay*

;
;	S	is not affected
;	Z	is not affected
;	H	is reset
;	P/V	is not affected
;	N	is reset
;	C	is data from bit 0 of Accumulator
;
; [note]
;	* "RR A"とはフラグ変化が異なることに注意してください。
;
z80cpu_RRA:
	ld.w %r12, %r0			; %t0 = 0:AAAAAAAA
	srl	%r0,0x1		; 	xsrl %r0, 1			; %A  = 0:0AAAAAAA
	ext	0x8		; 	xand %r13, %r1, 0x08		; %t1 = 0:0000C000
	and	%r13,%r1
	sll	%r13,0x4	; 	xsll %r13, 0x4			; %t1 = 0:C0000000
	or   %r0, %r13			; %t1 = 0:CAAAAAAA
	;
	and	%r1,0x7		; 	xand %r1, %r1, 0x7		; %F  = F(00000PZS)
	sll	%r12,0x3	; 	xsll %r12, 0x3			; %F  = A:AAAAA000
	and	%r12,0x8	; 	xand %r12, %r12, 0x08		; %F  = 0:0000A000
	or   %r1, %r12			; %F  = F(0000CPZS)
	ret.d
	sub %r3, 4		; *delay*

;
;	S	is not affected
;	Z	is not affected
;	H	is reset
;	P/V	is not affected
;	N	is reset
;	C	is data from bit 0 of Accumulator
;
; [note]
;	* "RRC A"とはフラグ変化が異なることに注意してください。
;
z80cpu_RRCA:
	ld.w  %r12, %r0			; %t0 = 0:AAAAAAAA
	ld.w  %r13, %r0			; %t1 = 0:AAAAAAAA
	srl	%r0,0x1		; 	xsrl  %r0, 1			; %A  = 0:0AAAAAAA
	sll	%r13,0x7	; 	xsll  %r13, 7			; %t1 = A:A0000000
	or    %r0, %r13			; %A  = A:AAAAAAAA
	ld.ub %r0, %r0			; %A  = 0:AAAAAAAA
	;
	and	%r1,0x7		; 	xand  %r1, %r1, 0x7		; %F  = F(00000PZS)
	sll	%r12,0x3	; 	xsll  %r12, 0x3			; %F  = A:AAAAA000
	and	%r12,0x8	; 	xand  %r12, %r12, 0x08		; %F  = 0:0000A000
	or    %r1, %r12			; %F  = F(0000CPZS)
	ret.d
	sub %r3, 4		; *delay*

;----------------------------------------------------------------------------

z80cpu_RL_A:
	ext	z80cpu_rl@rm	; 	xcall.d z80cpu_rl
	call.d	z80cpu_rl@rl
	ld.w %r10, %r0			; %a0 = A *delay*
	ld.w %r0, %r10			; %A = RL A
	ret.d
	sub %r3, 8		; *delay*

;#macro RL_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xcall z80cpu_rl
;	xld.b [%CPU+$2], %a0		; r = RL r
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_RL_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	RL_r CYCLE_RL_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_rl@rm	; 	xcall z80cpu_rl
	call	z80cpu_rl@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; r = RL r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RL_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	RL_r CYCLE_RL_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_rl@rm	; 	xcall z80cpu_rl
	call	z80cpu_rl@rl
	ext	0x2		; 	xld.b [%r4+0x2], %r10		; r = RL r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RL_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	RL_r CYCLE_RL_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_rl@rm	; 	xcall z80cpu_rl
	call	z80cpu_rl@rl
	ext	0x5		; 	xld.b [%r4+0x5], %r10		; r = RL r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RL_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	RL_r CYCLE_RL_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_rl@rm	; 	xcall z80cpu_rl
	call	z80cpu_rl@rl
	ext	0x4		; 	xld.b [%r4+0x4], %r10		; r = RL r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RL_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	RL_r CYCLE_RL_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_rl@rm	; 	xcall z80cpu_rl
	call	z80cpu_rl@rl
	ext	0x7		; 	xld.b [%r4+0x7], %r10		; r = RL r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RL_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	RL_r CYCLE_RL_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_rl@rm	; 	xcall z80cpu_rl
	call	z80cpu_rl@rl
	ext	0x6		; 	xld.b [%r4+0x6], %r10		; r = RL r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*

z80cpu_RL_IHLI:
	ext	0x6		; 	xld.uh %r6, [%r4+0x6]		; %s0 = HL
	ld.uh	%r6,[%r4]
	add    %r6, %r5		; %s0 = mem+HL
	ld.ub  %r10, [%r6]		; %a0 = [mem+HL]
	ext	z80cpu_rl@rm	; 	xcall z80cpu_rl
	call	z80cpu_rl@rl
	ld.b  [%r6], %r10		; [mem+HL] = RL [mem+HL]
	ret.d
	sub %r3, 15	; *delay*

z80cpu_RL_IaddrI:
	ld.ub %r10, [%r6]		; %a0 = [addr]
	ext	z80cpu_rl@rm	; 	xcall z80cpu_rl
	call	z80cpu_rl@rl
	ld.b [%r6], %r10			; [addr] = RL [addr]
	ret.d
	sub %r3, 23	; *delay*

;----------------------------------------------------------------------------

z80cpu_RLC_A:
	ext	z80cpu_rlc@rm	; 	xcall.d z80cpu_rlc
	call.d	z80cpu_rlc@rl
	ld.w %r10, %r0			; %a0 = A *delay*
	ld.w %r0, %r10			; %A = RLC A
	ret.d
	sub %r3, 8	; *delay*

;#macro RLC_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xcall z80cpu_rlc
;	xld.b [%CPU+$2], %a0		; r = RLC r
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_RLC_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	RLC_r CYCLE_RLC_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_rlc@rm	; 	xcall z80cpu_rlc
	call	z80cpu_rlc@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; r = RLC r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RLC_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	RLC_r CYCLE_RLC_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_rlc@rm	; 	xcall z80cpu_rlc
	call	z80cpu_rlc@rl
	ext	0x2		; 	xld.b [%r4+0x2], %r10		; r = RLC r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RLC_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	RLC_r CYCLE_RLC_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_rlc@rm	; 	xcall z80cpu_rlc
	call	z80cpu_rlc@rl
	ext	0x5		; 	xld.b [%r4+0x5], %r10		; r = RLC r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RLC_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	RLC_r CYCLE_RLC_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_rlc@rm	; 	xcall z80cpu_rlc
	call	z80cpu_rlc@rl
	ext	0x4		; 	xld.b [%r4+0x4], %r10		; r = RLC r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RLC_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	RLC_r CYCLE_RLC_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_rlc@rm	; 	xcall z80cpu_rlc
	call	z80cpu_rlc@rl
	ext	0x7		; 	xld.b [%r4+0x7], %r10		; r = RLC r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RLC_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	RLC_r CYCLE_RLC_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_rlc@rm	; 	xcall z80cpu_rlc
	call	z80cpu_rlc@rl
	ext	0x6		; 	xld.b [%r4+0x6], %r10		; r = RLC r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*

z80cpu_RLC_IHLI:
	ext	0x6		; 	xld.uh %r6, [%r4+0x6]		; %s0 = HL
	ld.uh	%r6,[%r4]
	add    %r6, %r5		; %s0 = mem+HL
	ld.ub  %r10, [%r6]		; %a0 = [mem+HL]
	ext	z80cpu_rlc@rm	; 	xcall z80cpu_rlc
	call	z80cpu_rlc@rl
	ld.b  [%r6], %r10		; [mem+HL] = RLC [mem+HL]
	ret.d
	sub %r3, 15	; *delay*

z80cpu_RLC_IaddrI:
	ld.ub %r10, [%r6]		; %a0 = [addr]
	ext	z80cpu_rlc@rm	; 	xcall z80cpu_rlc
	call	z80cpu_rlc@rl
	ld.b [%r6], %r10			; [addr] = RLC [addr]
	ret.d
	sub %r3, 23	; *delay*

;----------------------------------------------------------------------------

z80cpu_RR_A:
	ext	z80cpu_rr@rm	; 	xcall.d z80cpu_rr
	call.d	z80cpu_rr@rl
	ld.w %r10, %r0			; %a0 = A *delay*
	ld.w %r0, %r10			; %A = RR A
	ret.d
	sub %r3, 8		; *delay*

;#macro RR_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xcall z80cpu_rr
;	xld.b [%CPU+$2], %a0		; r = RR r
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_RR_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	RR_r CYCLE_RR_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_rr@rm	; 	xcall z80cpu_rr
	call	z80cpu_rr@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; r = RR r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RR_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	RR_r CYCLE_RR_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_rr@rm	; 	xcall z80cpu_rr
	call	z80cpu_rr@rl
	ext	0x2		; 	xld.b [%r4+0x2], %r10		; r = RR r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RR_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	RR_r CYCLE_RR_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_rr@rm	; 	xcall z80cpu_rr
	call	z80cpu_rr@rl
	ext	0x5		; 	xld.b [%r4+0x5], %r10		; r = RR r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RR_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	RR_r CYCLE_RR_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_rr@rm	; 	xcall z80cpu_rr
	call	z80cpu_rr@rl
	ext	0x4		; 	xld.b [%r4+0x4], %r10		; r = RR r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RR_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	RR_r CYCLE_RR_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_rr@rm	; 	xcall z80cpu_rr
	call	z80cpu_rr@rl
	ext	0x7		; 	xld.b [%r4+0x7], %r10		; r = RR r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RR_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	RR_r CYCLE_RR_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_rr@rm	; 	xcall z80cpu_rr
	call	z80cpu_rr@rl
	ext	0x6		; 	xld.b [%r4+0x6], %r10		; r = RR r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*

z80cpu_RR_IHLI:
	ext	0x6		; 	xld.uh %r6, [%r4+0x6]		; %s0 = HL
	ld.uh	%r6,[%r4]
	add    %r6, %r5		; %s0 = mem+HL
	ld.ub  %r10, [%r6]		; %a0 = [mem+HL]
	ext	z80cpu_rr@rm	; 	xcall z80cpu_rr
	call	z80cpu_rr@rl
	ld.b  [%r6], %r10		; [mem+HL] = RR [mem+HL]
	ret.d
	sub %r3, 15	; *delay*

z80cpu_RR_IaddrI:
	ld.ub %r10, [%r6]		; %a0 = [addr]
	ext	z80cpu_rr@rm	; 	xcall z80cpu_rr
	call	z80cpu_rr@rl
	ld.b [%r6], %r10			; [addr] = RR [addr]
	ret.d
	sub %r3, 23	; *delay*

;----------------------------------------------------------------------------

z80cpu_RRC_A:
	ext	z80cpu_rrc@rm	; 	xcall.d z80cpu_rrc
	call.d	z80cpu_rrc@rl
	ld.w %r10, %r0			; %a0 = A *delay*
	ld.w %r0, %r10			; %A = RRC A
	ret.d
	sub %r3, 8	; *delay*

;#macro RRC_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xcall z80cpu_rrc
;	xld.b [%CPU+$2], %a0		; r = RRC r
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_RRC_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	RRC_r CYCLE_RRC_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_rrc@rm	; 	xcall z80cpu_rrc
	call	z80cpu_rrc@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; r = RRC r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RRC_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	RRC_r CYCLE_RRC_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_rrc@rm	; 	xcall z80cpu_rrc
	call	z80cpu_rrc@rl
	ext	0x2		; 	xld.b [%r4+0x2], %r10		; r = RRC r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RRC_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	RRC_r CYCLE_RRC_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_rrc@rm	; 	xcall z80cpu_rrc
	call	z80cpu_rrc@rl
	ext	0x5		; 	xld.b [%r4+0x5], %r10		; r = RRC r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RRC_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	RRC_r CYCLE_RRC_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_rrc@rm	; 	xcall z80cpu_rrc
	call	z80cpu_rrc@rl
	ext	0x4		; 	xld.b [%r4+0x4], %r10		; r = RRC r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RRC_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	RRC_r CYCLE_RRC_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_rrc@rm	; 	xcall z80cpu_rrc
	call	z80cpu_rrc@rl
	ext	0x7		; 	xld.b [%r4+0x7], %r10		; r = RRC r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RRC_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	RRC_r CYCLE_RRC_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_rrc@rm	; 	xcall z80cpu_rrc
	call	z80cpu_rrc@rl
	ext	0x6		; 	xld.b [%r4+0x6], %r10		; r = RRC r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*

z80cpu_RRC_IHLI:
	ext	0x6		; 	xld.uh %r6, [%r4+0x6]		; %s0 = HL
	ld.uh	%r6,[%r4]
	add    %r6, %r5		; %s0 = mem+HL
	ld.ub  %r10, [%r6]		; %a0 = [mem+HL]
	ext	z80cpu_rrc@rm	; 	xcall z80cpu_rrc
	call	z80cpu_rrc@rl
	ld.b  [%r6], %r10		; [mem+HL] = RRC [mem+HL]
	ret.d
	sub %r3, 15	; *delay*

z80cpu_RRC_IaddrI:
	ld.ub %r10, [%r6]		; %a0 = [addr]
	ext	z80cpu_rrc@rm	; 	xcall z80cpu_rrc
	call	z80cpu_rrc@rl
	ld.b [%r6], %r10			; [addr] = RRC [addr]
	ret.d
	sub %r3, 23	; *delay*

;----------------------------------------------------------------------------

z80cpu_SLA_A:
	ext	z80cpu_sla@rm	; 	xcall.d z80cpu_sla
	call.d	z80cpu_sla@rl
	ld.w %r10, %r0			; %a0 = A *delay*
	ld.w %r0, %r10			; %A = SLA A
	ret.d
	sub %r3, 8		; *delay*

;#macro SLA_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xcall z80cpu_sla
;	xld.b [%CPU+$2], %a0		; r = SLA r
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_SLA_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	SLA_r CYCLE_SLA_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_sla@rm	; 	xcall z80cpu_sla
	call	z80cpu_sla@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; r = SLA r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SLA_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	SLA_r CYCLE_SLA_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_sla@rm	; 	xcall z80cpu_sla
	call	z80cpu_sla@rl
	ext	0x2		; 	xld.b [%r4+0x2], %r10		; r = SLA r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SLA_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	SLA_r CYCLE_SLA_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_sla@rm	; 	xcall z80cpu_sla
	call	z80cpu_sla@rl
	ext	0x5		; 	xld.b [%r4+0x5], %r10		; r = SLA r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SLA_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	SLA_r CYCLE_SLA_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_sla@rm	; 	xcall z80cpu_sla
	call	z80cpu_sla@rl
	ext	0x4		; 	xld.b [%r4+0x4], %r10		; r = SLA r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SLA_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	SLA_r CYCLE_SLA_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_sla@rm	; 	xcall z80cpu_sla
	call	z80cpu_sla@rl
	ext	0x7		; 	xld.b [%r4+0x7], %r10		; r = SLA r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SLA_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	SLA_r CYCLE_SLA_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_sla@rm	; 	xcall z80cpu_sla
	call	z80cpu_sla@rl
	ext	0x6		; 	xld.b [%r4+0x6], %r10		; r = SLA r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*

z80cpu_SLA_IHLI:
	ext	0x6		; 	xld.uh %r6, [%r4+0x6]		; %s0 = HL
	ld.uh	%r6,[%r4]
	add    %r6, %r5		; %s0 = mem+HL
	ld.ub  %r10, [%r6]		; %a0 = [mem+HL]
	ext	z80cpu_sla@rm	; 	xcall z80cpu_sla
	call	z80cpu_sla@rl
	ld.b  [%r6], %r10		; [mem+HL] = SLA [mem+HL]
	ret.d
	sub %r3, 15	; *delay*

z80cpu_SLA_IaddrI:
	ld.ub %r10, [%r6]		; %a0 = [addr]
	ext	z80cpu_sla@rm	; 	xcall z80cpu_sla
	call	z80cpu_sla@rl
	ld.b [%r6], %r10			; [addr] = SLA [addr]
	ret.d
	sub %r3, 23	; *delay*

;----------------------------------------------------------------------------

z80cpu_SRA_A:
	ext	z80cpu_sra@rm	; 	xcall.d z80cpu_sra
	call.d	z80cpu_sra@rl
	ld.w %r10, %r0			; %a0 = A *delay*
	ld.w %r0, %r10			; %a0 = SRA A
	ret.d
	sub %r3, 8		; *delay*

;#macro SRA_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = [addr]
;	xcall z80cpu_sra
;	xld.b [%CPU+$2], %a0		; [addr] = SRA [mem+HL]
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_SRA_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = [addr]	; 	SRA_r CYCLE_SRA_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_sra@rm	; 	xcall z80cpu_sra
	call	z80cpu_sra@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; [addr] = SRA [mem+HL]
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SRA_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = [addr]	; 	SRA_r CYCLE_SRA_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_sra@rm	; 	xcall z80cpu_sra
	call	z80cpu_sra@rl
	ext	0x2		; 	xld.b [%r4+0x2], %r10		; [addr] = SRA [mem+HL]
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SRA_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = [addr]	; 	SRA_r CYCLE_SRA_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_sra@rm	; 	xcall z80cpu_sra
	call	z80cpu_sra@rl
	ext	0x5		; 	xld.b [%r4+0x5], %r10		; [addr] = SRA [mem+HL]
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SRA_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = [addr]	; 	SRA_r CYCLE_SRA_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_sra@rm	; 	xcall z80cpu_sra
	call	z80cpu_sra@rl
	ext	0x4		; 	xld.b [%r4+0x4], %r10		; [addr] = SRA [mem+HL]
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SRA_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = [addr]	; 	SRA_r CYCLE_SRA_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_sra@rm	; 	xcall z80cpu_sra
	call	z80cpu_sra@rl
	ext	0x7		; 	xld.b [%r4+0x7], %r10		; [addr] = SRA [mem+HL]
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SRA_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = [addr]	; 	SRA_r CYCLE_SRA_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_sra@rm	; 	xcall z80cpu_sra
	call	z80cpu_sra@rl
	ext	0x6		; 	xld.b [%r4+0x6], %r10		; [addr] = SRA [mem+HL]
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*

z80cpu_SRA_IHLI:
	ext	0x6		; 	xld.uh %r6, [%r4+0x6]		; %s0 = HL
	ld.uh	%r6,[%r4]
	add    %r6, %r5		; %s0 = mem+HL
	ld.ub  %r10, [%r6]		; %a0 = [mem+HL]
	ext	z80cpu_sra@rm	; 	xcall z80cpu_sra
	call	z80cpu_sra@rl
	ld.b  [%r6], %r10		; [mem+HL] = SRA [mem+HL]
	ret.d
	sub %r3, 15	; *delay*

z80cpu_SRA_IaddrI:
	ld.ub %r10, [%r6]		; %a0 = [addr]
	ext	z80cpu_sra@rm	; 	xcall z80cpu_sra
	call	z80cpu_sra@rl
	ld.b [%r6], %r10			; [addr] = SRA [addr]
	ret.d
	sub %r3, 23	; *delay*

;----------------------------------------------------------------------------

z80cpu_SRL_A:
	ext	z80cpu_srl@rm	; 	xcall.d z80cpu_srl
	call.d	z80cpu_srl@rl
	ld.w %r10, %r0			; %a0 = A *delay*
	ld.w %r0, %r10			; %A = SRL A
	ret.d
	sub %r3, 8		; *delay*

;#macro SRL_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xcall z80cpu_srl
;	xld.b [%CPU+$2], %a0		; r = SRL r
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_SRL_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	SRL_r CYCLE_SRL_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_srl@rm	; 	xcall z80cpu_srl
	call	z80cpu_srl@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; r = SRL r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SRL_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	SRL_r CYCLE_SRL_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_srl@rm	; 	xcall z80cpu_srl
	call	z80cpu_srl@rl
	ext	0x2		; 	xld.b [%r4+0x2], %r10		; r = SRL r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SRL_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	SRL_r CYCLE_SRL_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_srl@rm	; 	xcall z80cpu_srl
	call	z80cpu_srl@rl
	ext	0x5		; 	xld.b [%r4+0x5], %r10		; r = SRL r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SRL_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	SRL_r CYCLE_SRL_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_srl@rm	; 	xcall z80cpu_srl
	call	z80cpu_srl@rl
	ext	0x4		; 	xld.b [%r4+0x4], %r10		; r = SRL r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SRL_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	SRL_r CYCLE_SRL_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_srl@rm	; 	xcall z80cpu_srl
	call	z80cpu_srl@rl
	ext	0x7		; 	xld.b [%r4+0x7], %r10		; r = SRL r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SRL_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	SRL_r CYCLE_SRL_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_srl@rm	; 	xcall z80cpu_srl
	call	z80cpu_srl@rl
	ext	0x6		; 	xld.b [%r4+0x6], %r10		; r = SRL r
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 8			; *delay*

z80cpu_SRL_IHLI:
	ext	0x6		; 	xld.uh %r6, [%r4+0x6]		; %s0 = HL
	ld.uh	%r6,[%r4]
	add    %r6, %r5		; %s0 = mem+HL
	ld.ub  %r10, [%r6]		; %a0 = [mem+HL]
	ext	z80cpu_srl@rm	; 	xcall z80cpu_srl
	call	z80cpu_srl@rl
	ld.b  [%r6], %r10		; [mem+HL] = SRL [mem+HL]
	ret.d
	sub %r3, 15	; *delay*

z80cpu_SRL_IaddrI:
	ld.ub %r10, [%r6]		; %a0 = [addr]
	ext	z80cpu_srl@rm	; 	xcall z80cpu_srl
	call	z80cpu_srl@rl
	ld.b [%r6], %r10			; [addr] = SRL [addr]
	ret.d
	sub %r3, 23	; *delay*

;----------------------------------------------------------------------------

;
; [note]
;	* 遅くても構わないので、C言語版を呼び出しています。
;	  いずれ、アセンブラ化する予定です。
;
z80cpu_RLD:
	ext	z80cpu_leave@rm	; 	xcall z80cpu_leave		; 実行コンテキストを書き戻します。
	call	z80cpu_leave@rl
	ext	z80cpu_rld@rm	; 	xcall z80cpu_rld
	call	z80cpu_rld@rl
	ext	z80cpu_enter@rm	; 	xjp.d z80cpu_enter		; 実行コンテキストを取り出します。
	jp.d	z80cpu_enter@rl
	sub %r3, 18		; *delay*

;
; [note]
;	* 遅くても構わないので、C言語版を呼び出しています。
;	  いずれ、アセンブラ化する予定です。
;
z80cpu_RRD:
	ext	z80cpu_leave@rm	; 	xcall z80cpu_leave		; 実行コンテキストを書き戻します。
	call	z80cpu_leave@rl
	ext	z80cpu_rrd@rm	; 	xcall z80cpu_rrd
	call	z80cpu_rrd@rl
	ext	z80cpu_enter@rm	; 	xjp.d z80cpu_enter		; 実行コンテキストを取り出します。
	jp.d	z80cpu_enter@rl
	sub %r3, 18		; *delay*

;****************************************************************************
;	Bit Set, Reset, and Test Group
;****************************************************************************

	.global z80cpu_BIT_0_A
	.global z80cpu_BIT_0_B
	.global z80cpu_BIT_0_C
	.global z80cpu_BIT_0_D
	.global z80cpu_BIT_0_E
	.global z80cpu_BIT_0_H
	.global z80cpu_BIT_0_L
	.global z80cpu_BIT_0_IHLI
	.global z80cpu_BIT_0_IaddrI
	.global z80cpu_BIT_1_A
	.global z80cpu_BIT_1_B
	.global z80cpu_BIT_1_C
	.global z80cpu_BIT_1_D
	.global z80cpu_BIT_1_E
	.global z80cpu_BIT_1_H
	.global z80cpu_BIT_1_L
	.global z80cpu_BIT_1_IHLI
	.global z80cpu_BIT_1_IaddrI
	.global z80cpu_BIT_2_A
	.global z80cpu_BIT_2_B
	.global z80cpu_BIT_2_C
	.global z80cpu_BIT_2_D
	.global z80cpu_BIT_2_E
	.global z80cpu_BIT_2_H
	.global z80cpu_BIT_2_L
	.global z80cpu_BIT_2_IHLI
	.global z80cpu_BIT_2_IaddrI
	.global z80cpu_BIT_3_A
	.global z80cpu_BIT_3_B
	.global z80cpu_BIT_3_C
	.global z80cpu_BIT_3_D
	.global z80cpu_BIT_3_E
	.global z80cpu_BIT_3_H
	.global z80cpu_BIT_3_L
	.global z80cpu_BIT_3_IHLI
	.global z80cpu_BIT_3_IaddrI
	.global z80cpu_BIT_4_A
	.global z80cpu_BIT_4_B
	.global z80cpu_BIT_4_C
	.global z80cpu_BIT_4_D
	.global z80cpu_BIT_4_E
	.global z80cpu_BIT_4_H
	.global z80cpu_BIT_4_L
	.global z80cpu_BIT_4_IHLI
	.global z80cpu_BIT_4_IaddrI
	.global z80cpu_BIT_5_A
	.global z80cpu_BIT_5_B
	.global z80cpu_BIT_5_C
	.global z80cpu_BIT_5_D
	.global z80cpu_BIT_5_E
	.global z80cpu_BIT_5_H
	.global z80cpu_BIT_5_L
	.global z80cpu_BIT_5_IHLI
	.global z80cpu_BIT_5_IaddrI
	.global z80cpu_BIT_6_A
	.global z80cpu_BIT_6_B
	.global z80cpu_BIT_6_C
	.global z80cpu_BIT_6_D
	.global z80cpu_BIT_6_E
	.global z80cpu_BIT_6_H
	.global z80cpu_BIT_6_L
	.global z80cpu_BIT_6_IHLI
	.global z80cpu_BIT_6_IaddrI
	.global z80cpu_BIT_7_A
	.global z80cpu_BIT_7_B
	.global z80cpu_BIT_7_C
	.global z80cpu_BIT_7_D
	.global z80cpu_BIT_7_E
	.global z80cpu_BIT_7_H
	.global z80cpu_BIT_7_L
	.global z80cpu_BIT_7_IHLI
	.global z80cpu_BIT_7_IaddrI

	.global z80cpu_SET_0_A
	.global z80cpu_SET_0_B
	.global z80cpu_SET_0_C
	.global z80cpu_SET_0_D
	.global z80cpu_SET_0_E
	.global z80cpu_SET_0_H
	.global z80cpu_SET_0_L
	.global z80cpu_SET_0_IHLI
	.global z80cpu_SET_0_IaddrI
	.global z80cpu_SET_1_A
	.global z80cpu_SET_1_B
	.global z80cpu_SET_1_C
	.global z80cpu_SET_1_D
	.global z80cpu_SET_1_E
	.global z80cpu_SET_1_H
	.global z80cpu_SET_1_L
	.global z80cpu_SET_1_IHLI
	.global z80cpu_SET_1_IaddrI
	.global z80cpu_SET_2_A
	.global z80cpu_SET_2_B
	.global z80cpu_SET_2_C
	.global z80cpu_SET_2_D
	.global z80cpu_SET_2_E
	.global z80cpu_SET_2_H
	.global z80cpu_SET_2_L
	.global z80cpu_SET_2_IHLI
	.global z80cpu_SET_2_IaddrI
	.global z80cpu_SET_3_A
	.global z80cpu_SET_3_B
	.global z80cpu_SET_3_C
	.global z80cpu_SET_3_D
	.global z80cpu_SET_3_E
	.global z80cpu_SET_3_H
	.global z80cpu_SET_3_L
	.global z80cpu_SET_3_IHLI
	.global z80cpu_SET_3_IaddrI
	.global z80cpu_SET_4_A
	.global z80cpu_SET_4_B
	.global z80cpu_SET_4_C
	.global z80cpu_SET_4_D
	.global z80cpu_SET_4_E
	.global z80cpu_SET_4_H
	.global z80cpu_SET_4_L
	.global z80cpu_SET_4_IHLI
	.global z80cpu_SET_4_IaddrI
	.global z80cpu_SET_5_A
	.global z80cpu_SET_5_B
	.global z80cpu_SET_5_C
	.global z80cpu_SET_5_D
	.global z80cpu_SET_5_E
	.global z80cpu_SET_5_H
	.global z80cpu_SET_5_L
	.global z80cpu_SET_5_IHLI
	.global z80cpu_SET_5_IaddrI
	.global z80cpu_SET_6_A
	.global z80cpu_SET_6_B
	.global z80cpu_SET_6_C
	.global z80cpu_SET_6_D
	.global z80cpu_SET_6_E
	.global z80cpu_SET_6_H
	.global z80cpu_SET_6_L
	.global z80cpu_SET_6_IHLI
	.global z80cpu_SET_6_IaddrI
	.global z80cpu_SET_7_A
	.global z80cpu_SET_7_B
	.global z80cpu_SET_7_C
	.global z80cpu_SET_7_D
	.global z80cpu_SET_7_E
	.global z80cpu_SET_7_H
	.global z80cpu_SET_7_L
	.global z80cpu_SET_7_IHLI
	.global z80cpu_SET_7_IaddrI

	.global z80cpu_RES_0_A
	.global z80cpu_RES_0_B
	.global z80cpu_RES_0_C
	.global z80cpu_RES_0_D
	.global z80cpu_RES_0_E
	.global z80cpu_RES_0_H
	.global z80cpu_RES_0_L
	.global z80cpu_RES_0_IHLI
	.global z80cpu_RES_0_IaddrI
	.global z80cpu_RES_1_A
	.global z80cpu_RES_1_B
	.global z80cpu_RES_1_C
	.global z80cpu_RES_1_D
	.global z80cpu_RES_1_E
	.global z80cpu_RES_1_H
	.global z80cpu_RES_1_L
	.global z80cpu_RES_1_IHLI
	.global z80cpu_RES_1_IaddrI
	.global z80cpu_RES_2_A
	.global z80cpu_RES_2_B
	.global z80cpu_RES_2_C
	.global z80cpu_RES_2_D
	.global z80cpu_RES_2_E
	.global z80cpu_RES_2_H
	.global z80cpu_RES_2_L
	.global z80cpu_RES_2_IHLI
	.global z80cpu_RES_2_IaddrI
	.global z80cpu_RES_3_A
	.global z80cpu_RES_3_B
	.global z80cpu_RES_3_C
	.global z80cpu_RES_3_D
	.global z80cpu_RES_3_E
	.global z80cpu_RES_3_H
	.global z80cpu_RES_3_L
	.global z80cpu_RES_3_IHLI
	.global z80cpu_RES_3_IaddrI
	.global z80cpu_RES_4_A
	.global z80cpu_RES_4_B
	.global z80cpu_RES_4_C
	.global z80cpu_RES_4_D
	.global z80cpu_RES_4_E
	.global z80cpu_RES_4_H
	.global z80cpu_RES_4_L
	.global z80cpu_RES_4_IHLI
	.global z80cpu_RES_4_IaddrI
	.global z80cpu_RES_5_A
	.global z80cpu_RES_5_B
	.global z80cpu_RES_5_C
	.global z80cpu_RES_5_D
	.global z80cpu_RES_5_E
	.global z80cpu_RES_5_H
	.global z80cpu_RES_5_L
	.global z80cpu_RES_5_IHLI
	.global z80cpu_RES_5_IaddrI
	.global z80cpu_RES_6_A
	.global z80cpu_RES_6_B
	.global z80cpu_RES_6_C
	.global z80cpu_RES_6_D
	.global z80cpu_RES_6_E
	.global z80cpu_RES_6_H
	.global z80cpu_RES_6_L
	.global z80cpu_RES_6_IHLI
	.global z80cpu_RES_6_IaddrI
	.global z80cpu_RES_7_A
	.global z80cpu_RES_7_B
	.global z80cpu_RES_7_C
	.global z80cpu_RES_7_D
	.global z80cpu_RES_7_E
	.global z80cpu_RES_7_H
	.global z80cpu_RES_7_L	
	.global z80cpu_RES_7_IHLI
	.global z80cpu_RES_7_IaddrI

;----------------------------------------------------------------------------

;#macro BIT_b_A $1, $2
;	xld.w %a0, $2			; %a0 = b
;	ld.w  %a1, %A			; %a1 = A
;	xjp.d z80cpu_bit
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_BIT_0_A:
	ld.w	%r10,0x0	; 	xld.w %r10, 0			; %a0 = b	; 	BIT_b_A CYCLE_BIT_0_A, 0
	ld.w  %r11, %r0			; %a1 = A
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_1_A:
	ld.w	%r10,0x1	; 	xld.w %r10, 1			; %a0 = b	; 	BIT_b_A CYCLE_BIT_1_A, 1
	ld.w  %r11, %r0			; %a1 = A
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_2_A:
	ld.w	%r10,0x2	; 	xld.w %r10, 2			; %a0 = b	; 	BIT_b_A CYCLE_BIT_2_A, 2
	ld.w  %r11, %r0			; %a1 = A
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_3_A:
	ld.w	%r10,0x3	; 	xld.w %r10, 3			; %a0 = b	; 	BIT_b_A CYCLE_BIT_3_A, 3
	ld.w  %r11, %r0			; %a1 = A
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_4_A:
	ld.w	%r10,0x4	; 	xld.w %r10, 4			; %a0 = b	; 	BIT_b_A CYCLE_BIT_4_A, 4
	ld.w  %r11, %r0			; %a1 = A
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_5_A:
	ld.w	%r10,0x5	; 	xld.w %r10, 5			; %a0 = b	; 	BIT_b_A CYCLE_BIT_5_A, 5
	ld.w  %r11, %r0			; %a1 = A
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_6_A:
	ld.w	%r10,0x6	; 	xld.w %r10, 6			; %a0 = b	; 	BIT_b_A CYCLE_BIT_6_A, 6
	ld.w  %r11, %r0			; %a1 = A
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_7_A:
	ld.w	%r10,0x7	; 	xld.w %r10, 7			; %a0 = b	; 	BIT_b_A CYCLE_BIT_7_A, 7
	ld.w  %r11, %r0			; %a1 = A
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*

;#macro BIT_b_r $1, $2, $3
;	xld.w  %a0, $2			; %a0 = b
;	xld.ub %a1, [%CPU+$3]		; %a1 = r
;	xjp.d z80cpu_bit
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_BIT_0_B:
	ld.w	%r10,0x0	; 	xld.w  %r10, 0			; %a0 = b	; 	BIT_b_r CYCLE_BIT_0_B, 0, B
	ext	0x3		; 	xld.ub %r11, [%r4+0x3]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_1_B:
	ld.w	%r10,0x1	; 	xld.w  %r10, 1			; %a0 = b	; 	BIT_b_r CYCLE_BIT_1_B, 1, B
	ext	0x3		; 	xld.ub %r11, [%r4+0x3]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_2_B:
	ld.w	%r10,0x2	; 	xld.w  %r10, 2			; %a0 = b	; 	BIT_b_r CYCLE_BIT_2_B, 2, B
	ext	0x3		; 	xld.ub %r11, [%r4+0x3]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_3_B:
	ld.w	%r10,0x3	; 	xld.w  %r10, 3			; %a0 = b	; 	BIT_b_r CYCLE_BIT_3_B, 3, B
	ext	0x3		; 	xld.ub %r11, [%r4+0x3]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_4_B:
	ld.w	%r10,0x4	; 	xld.w  %r10, 4			; %a0 = b	; 	BIT_b_r CYCLE_BIT_4_B, 4, B
	ext	0x3		; 	xld.ub %r11, [%r4+0x3]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_5_B:
	ld.w	%r10,0x5	; 	xld.w  %r10, 5			; %a0 = b	; 	BIT_b_r CYCLE_BIT_5_B, 5, B
	ext	0x3		; 	xld.ub %r11, [%r4+0x3]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_6_B:
	ld.w	%r10,0x6	; 	xld.w  %r10, 6			; %a0 = b	; 	BIT_b_r CYCLE_BIT_6_B, 6, B
	ext	0x3		; 	xld.ub %r11, [%r4+0x3]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_7_B:
	ld.w	%r10,0x7	; 	xld.w  %r10, 7			; %a0 = b	; 	BIT_b_r CYCLE_BIT_7_B, 7, B
	ext	0x3		; 	xld.ub %r11, [%r4+0x3]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*

z80cpu_BIT_0_C:
	ld.w	%r10,0x0	; 	xld.w  %r10, 0			; %a0 = b	; 	BIT_b_r CYCLE_BIT_0_C, 0, C
	ext	0x2		; 	xld.ub %r11, [%r4+0x2]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_1_C:
	ld.w	%r10,0x1	; 	xld.w  %r10, 1			; %a0 = b	; 	BIT_b_r CYCLE_BIT_1_C, 1, C
	ext	0x2		; 	xld.ub %r11, [%r4+0x2]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_2_C:
	ld.w	%r10,0x2	; 	xld.w  %r10, 2			; %a0 = b	; 	BIT_b_r CYCLE_BIT_2_C, 2, C
	ext	0x2		; 	xld.ub %r11, [%r4+0x2]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_3_C:
	ld.w	%r10,0x3	; 	xld.w  %r10, 3			; %a0 = b	; 	BIT_b_r CYCLE_BIT_3_C, 3, C
	ext	0x2		; 	xld.ub %r11, [%r4+0x2]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_4_C:
	ld.w	%r10,0x4	; 	xld.w  %r10, 4			; %a0 = b	; 	BIT_b_r CYCLE_BIT_4_C, 4, C
	ext	0x2		; 	xld.ub %r11, [%r4+0x2]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_5_C:
	ld.w	%r10,0x5	; 	xld.w  %r10, 5			; %a0 = b	; 	BIT_b_r CYCLE_BIT_5_C, 5, C
	ext	0x2		; 	xld.ub %r11, [%r4+0x2]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_6_C:
	ld.w	%r10,0x6	; 	xld.w  %r10, 6			; %a0 = b	; 	BIT_b_r CYCLE_BIT_6_C, 6, C
	ext	0x2		; 	xld.ub %r11, [%r4+0x2]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_7_C:
	ld.w	%r10,0x7	; 	xld.w  %r10, 7			; %a0 = b	; 	BIT_b_r CYCLE_BIT_7_C, 7, C
	ext	0x2		; 	xld.ub %r11, [%r4+0x2]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*

z80cpu_BIT_0_D:
	ld.w	%r10,0x0	; 	xld.w  %r10, 0			; %a0 = b	; 	BIT_b_r CYCLE_BIT_0_D, 0, D
	ext	0x5		; 	xld.ub %r11, [%r4+0x5]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_1_D:
	ld.w	%r10,0x1	; 	xld.w  %r10, 1			; %a0 = b	; 	BIT_b_r CYCLE_BIT_1_D, 1, D
	ext	0x5		; 	xld.ub %r11, [%r4+0x5]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_2_D:
	ld.w	%r10,0x2	; 	xld.w  %r10, 2			; %a0 = b	; 	BIT_b_r CYCLE_BIT_2_D, 2, D
	ext	0x5		; 	xld.ub %r11, [%r4+0x5]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_3_D:
	ld.w	%r10,0x3	; 	xld.w  %r10, 3			; %a0 = b	; 	BIT_b_r CYCLE_BIT_3_D, 3, D
	ext	0x5		; 	xld.ub %r11, [%r4+0x5]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_4_D:
	ld.w	%r10,0x4	; 	xld.w  %r10, 4			; %a0 = b	; 	BIT_b_r CYCLE_BIT_4_D, 4, D
	ext	0x5		; 	xld.ub %r11, [%r4+0x5]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_5_D:
	ld.w	%r10,0x5	; 	xld.w  %r10, 5			; %a0 = b	; 	BIT_b_r CYCLE_BIT_5_D, 5, D
	ext	0x5		; 	xld.ub %r11, [%r4+0x5]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_6_D:
	ld.w	%r10,0x6	; 	xld.w  %r10, 6			; %a0 = b	; 	BIT_b_r CYCLE_BIT_6_D, 6, D
	ext	0x5		; 	xld.ub %r11, [%r4+0x5]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_7_D:
	ld.w	%r10,0x7	; 	xld.w  %r10, 7			; %a0 = b	; 	BIT_b_r CYCLE_BIT_7_D, 7, D
	ext	0x5		; 	xld.ub %r11, [%r4+0x5]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*

z80cpu_BIT_0_E:
	ld.w	%r10,0x0	; 	xld.w  %r10, 0			; %a0 = b	; 	BIT_b_r CYCLE_BIT_0_E, 0, E
	ext	0x4		; 	xld.ub %r11, [%r4+0x4]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_1_E:
	ld.w	%r10,0x1	; 	xld.w  %r10, 1			; %a0 = b	; 	BIT_b_r CYCLE_BIT_1_E, 1, E
	ext	0x4		; 	xld.ub %r11, [%r4+0x4]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_2_E:
	ld.w	%r10,0x2	; 	xld.w  %r10, 2			; %a0 = b	; 	BIT_b_r CYCLE_BIT_2_E, 2, E
	ext	0x4		; 	xld.ub %r11, [%r4+0x4]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_3_E:
	ld.w	%r10,0x3	; 	xld.w  %r10, 3			; %a0 = b	; 	BIT_b_r CYCLE_BIT_3_E, 3, E
	ext	0x4		; 	xld.ub %r11, [%r4+0x4]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_4_E:
	ld.w	%r10,0x4	; 	xld.w  %r10, 4			; %a0 = b	; 	BIT_b_r CYCLE_BIT_4_E, 4, E
	ext	0x4		; 	xld.ub %r11, [%r4+0x4]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_5_E:
	ld.w	%r10,0x5	; 	xld.w  %r10, 5			; %a0 = b	; 	BIT_b_r CYCLE_BIT_5_E, 5, E
	ext	0x4		; 	xld.ub %r11, [%r4+0x4]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_6_E:
	ld.w	%r10,0x6	; 	xld.w  %r10, 6			; %a0 = b	; 	BIT_b_r CYCLE_BIT_6_E, 6, E
	ext	0x4		; 	xld.ub %r11, [%r4+0x4]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_7_E:
	ld.w	%r10,0x7	; 	xld.w  %r10, 7			; %a0 = b	; 	BIT_b_r CYCLE_BIT_7_E, 7, E
	ext	0x4		; 	xld.ub %r11, [%r4+0x4]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*

z80cpu_BIT_0_H:
	ld.w	%r10,0x0	; 	xld.w  %r10, 0			; %a0 = b	; 	BIT_b_r CYCLE_BIT_0_H, 0, H
	ext	0x7		; 	xld.ub %r11, [%r4+0x7]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_1_H:
	ld.w	%r10,0x1	; 	xld.w  %r10, 1			; %a0 = b	; 	BIT_b_r CYCLE_BIT_1_H, 1, H
	ext	0x7		; 	xld.ub %r11, [%r4+0x7]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_2_H:
	ld.w	%r10,0x2	; 	xld.w  %r10, 2			; %a0 = b	; 	BIT_b_r CYCLE_BIT_2_H, 2, H
	ext	0x7		; 	xld.ub %r11, [%r4+0x7]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_3_H:
	ld.w	%r10,0x3	; 	xld.w  %r10, 3			; %a0 = b	; 	BIT_b_r CYCLE_BIT_3_H, 3, H
	ext	0x7		; 	xld.ub %r11, [%r4+0x7]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_4_H:
	ld.w	%r10,0x4	; 	xld.w  %r10, 4			; %a0 = b	; 	BIT_b_r CYCLE_BIT_4_H, 4, H
	ext	0x7		; 	xld.ub %r11, [%r4+0x7]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_5_H:
	ld.w	%r10,0x5	; 	xld.w  %r10, 5			; %a0 = b	; 	BIT_b_r CYCLE_BIT_5_H, 5, H
	ext	0x7		; 	xld.ub %r11, [%r4+0x7]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_6_H:
	ld.w	%r10,0x6	; 	xld.w  %r10, 6			; %a0 = b	; 	BIT_b_r CYCLE_BIT_6_H, 6, H
	ext	0x7		; 	xld.ub %r11, [%r4+0x7]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_7_H:
	ld.w	%r10,0x7	; 	xld.w  %r10, 7			; %a0 = b	; 	BIT_b_r CYCLE_BIT_7_H, 7, H
	ext	0x7		; 	xld.ub %r11, [%r4+0x7]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*

z80cpu_BIT_0_L:
	ld.w	%r10,0x0	; 	xld.w  %r10, 0			; %a0 = b	; 	BIT_b_r CYCLE_BIT_0_L, 0, L
	ext	0x6		; 	xld.ub %r11, [%r4+0x6]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_1_L:
	ld.w	%r10,0x1	; 	xld.w  %r10, 1			; %a0 = b	; 	BIT_b_r CYCLE_BIT_1_L, 1, L
	ext	0x6		; 	xld.ub %r11, [%r4+0x6]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_2_L:
	ld.w	%r10,0x2	; 	xld.w  %r10, 2			; %a0 = b	; 	BIT_b_r CYCLE_BIT_2_L, 2, L
	ext	0x6		; 	xld.ub %r11, [%r4+0x6]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_3_L:
	ld.w	%r10,0x3	; 	xld.w  %r10, 3			; %a0 = b	; 	BIT_b_r CYCLE_BIT_3_L, 3, L
	ext	0x6		; 	xld.ub %r11, [%r4+0x6]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_4_L:
	ld.w	%r10,0x4	; 	xld.w  %r10, 4			; %a0 = b	; 	BIT_b_r CYCLE_BIT_4_L, 4, L
	ext	0x6		; 	xld.ub %r11, [%r4+0x6]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_5_L:
	ld.w	%r10,0x5	; 	xld.w  %r10, 5			; %a0 = b	; 	BIT_b_r CYCLE_BIT_5_L, 5, L
	ext	0x6		; 	xld.ub %r11, [%r4+0x6]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_6_L:
	ld.w	%r10,0x6	; 	xld.w  %r10, 6			; %a0 = b	; 	BIT_b_r CYCLE_BIT_6_L, 6, L
	ext	0x6		; 	xld.ub %r11, [%r4+0x6]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*
z80cpu_BIT_7_L:
	ld.w	%r10,0x7	; 	xld.w  %r10, 7			; %a0 = b	; 	BIT_b_r CYCLE_BIT_7_L, 7, L
	ext	0x6		; 	xld.ub %r11, [%r4+0x6]		; %a1 = r
	ld.ub	%r11,[%r4]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 8			; *delay*

;#macro BIT_b_IHLI $1, $2
;	xld.w  %a0, $2			; %a0 = b
;	xld.uh %a1, [%CPU+HL]		; %a1 = HL
;	add    %a1, %MEM		; %a1 = mem+HL
;	ld.ub  %a1, [%a1]		; %a1 = [mem+HL]
;	xjp.d z80cpu_bit
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_BIT_0_IHLI:
	ld.w	%r10,0x0	; 	xld.w  %r10, 0			; %a0 = b	; 	BIT_b_IHLI CYCLE_BIT_0_IHLI, 0
	ext	0x6		; 	xld.uh %r11, [%r4+0x6]		; %a1 = HL
	ld.uh	%r11,[%r4]
	add    %r11, %r5		; %a1 = mem+HL
	ld.ub  %r11, [%r11]		; %a1 = [mem+HL]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 12			; *delay*
z80cpu_BIT_1_IHLI:
	ld.w	%r10,0x1	; 	xld.w  %r10, 1			; %a0 = b	; 	BIT_b_IHLI CYCLE_BIT_1_IHLI, 1
	ext	0x6		; 	xld.uh %r11, [%r4+0x6]		; %a1 = HL
	ld.uh	%r11,[%r4]
	add    %r11, %r5		; %a1 = mem+HL
	ld.ub  %r11, [%r11]		; %a1 = [mem+HL]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 12			; *delay*
z80cpu_BIT_2_IHLI:
	ld.w	%r10,0x2	; 	xld.w  %r10, 2			; %a0 = b	; 	BIT_b_IHLI CYCLE_BIT_2_IHLI, 2
	ext	0x6		; 	xld.uh %r11, [%r4+0x6]		; %a1 = HL
	ld.uh	%r11,[%r4]
	add    %r11, %r5		; %a1 = mem+HL
	ld.ub  %r11, [%r11]		; %a1 = [mem+HL]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 12			; *delay*
z80cpu_BIT_3_IHLI:
	ld.w	%r10,0x3	; 	xld.w  %r10, 3			; %a0 = b	; 	BIT_b_IHLI CYCLE_BIT_3_IHLI, 3
	ext	0x6		; 	xld.uh %r11, [%r4+0x6]		; %a1 = HL
	ld.uh	%r11,[%r4]
	add    %r11, %r5		; %a1 = mem+HL
	ld.ub  %r11, [%r11]		; %a1 = [mem+HL]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 12			; *delay*
z80cpu_BIT_4_IHLI:
	ld.w	%r10,0x4	; 	xld.w  %r10, 4			; %a0 = b	; 	BIT_b_IHLI CYCLE_BIT_4_IHLI, 4
	ext	0x6		; 	xld.uh %r11, [%r4+0x6]		; %a1 = HL
	ld.uh	%r11,[%r4]
	add    %r11, %r5		; %a1 = mem+HL
	ld.ub  %r11, [%r11]		; %a1 = [mem+HL]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 12			; *delay*
z80cpu_BIT_5_IHLI:
	ld.w	%r10,0x5	; 	xld.w  %r10, 5			; %a0 = b	; 	BIT_b_IHLI CYCLE_BIT_5_IHLI, 5
	ext	0x6		; 	xld.uh %r11, [%r4+0x6]		; %a1 = HL
	ld.uh	%r11,[%r4]
	add    %r11, %r5		; %a1 = mem+HL
	ld.ub  %r11, [%r11]		; %a1 = [mem+HL]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 12			; *delay*
z80cpu_BIT_6_IHLI:
	ld.w	%r10,0x6	; 	xld.w  %r10, 6			; %a0 = b	; 	BIT_b_IHLI CYCLE_BIT_6_IHLI, 6
	ext	0x6		; 	xld.uh %r11, [%r4+0x6]		; %a1 = HL
	ld.uh	%r11,[%r4]
	add    %r11, %r5		; %a1 = mem+HL
	ld.ub  %r11, [%r11]		; %a1 = [mem+HL]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 12			; *delay*
z80cpu_BIT_7_IHLI:
	ld.w	%r10,0x7	; 	xld.w  %r10, 7			; %a0 = b	; 	BIT_b_IHLI CYCLE_BIT_7_IHLI, 7
	ext	0x6		; 	xld.uh %r11, [%r4+0x6]		; %a1 = HL
	ld.uh	%r11,[%r4]
	add    %r11, %r5		; %a1 = mem+HL
	ld.ub  %r11, [%r11]		; %a1 = [mem+HL]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 12			; *delay*

;#macro BIT_b_IaddrI $1, $2
;	xld.w %a0, $2			; %a0 = b
;	ld.ub %a1, [%s0]		; %a1 = [addr]
;	xjp.d z80cpu_bit
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_BIT_0_IaddrI:
	ld.w	%r10,0x0	; 	xld.w %r10, 0			; %a0 = b	; 	BIT_b_IaddrI CYCLE_BIT_0_IaddrI, 0
	ld.ub %r11, [%r6]		; %a1 = [addr]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 20			; *delay*
z80cpu_BIT_1_IaddrI:
	ld.w	%r10,0x1	; 	xld.w %r10, 1			; %a0 = b	; 	BIT_b_IaddrI CYCLE_BIT_1_IaddrI, 1
	ld.ub %r11, [%r6]		; %a1 = [addr]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 20			; *delay*
z80cpu_BIT_2_IaddrI:
	ld.w	%r10,0x2	; 	xld.w %r10, 2			; %a0 = b	; 	BIT_b_IaddrI CYCLE_BIT_2_IaddrI, 2
	ld.ub %r11, [%r6]		; %a1 = [addr]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 20			; *delay*
z80cpu_BIT_3_IaddrI:
	ld.w	%r10,0x3	; 	xld.w %r10, 3			; %a0 = b	; 	BIT_b_IaddrI CYCLE_BIT_3_IaddrI, 3
	ld.ub %r11, [%r6]		; %a1 = [addr]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 20			; *delay*
z80cpu_BIT_4_IaddrI:
	ld.w	%r10,0x4	; 	xld.w %r10, 4			; %a0 = b	; 	BIT_b_IaddrI CYCLE_BIT_4_IaddrI, 4
	ld.ub %r11, [%r6]		; %a1 = [addr]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 20			; *delay*
z80cpu_BIT_5_IaddrI:
	ld.w	%r10,0x5	; 	xld.w %r10, 5			; %a0 = b	; 	BIT_b_IaddrI CYCLE_BIT_5_IaddrI, 5
	ld.ub %r11, [%r6]		; %a1 = [addr]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 20			; *delay*
z80cpu_BIT_6_IaddrI:
	ld.w	%r10,0x6	; 	xld.w %r10, 6			; %a0 = b	; 	BIT_b_IaddrI CYCLE_BIT_6_IaddrI, 6
	ld.ub %r11, [%r6]		; %a1 = [addr]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 20			; *delay*
z80cpu_BIT_7_IaddrI:
	ld.w	%r10,0x7	; 	xld.w %r10, 7			; %a0 = b	; 	BIT_b_IaddrI CYCLE_BIT_7_IaddrI, 7
	ld.ub %r11, [%r6]		; %a1 = [addr]
	ext	z80cpu_bit@rm	; 	xjp.d z80cpu_bit
	jp.d	z80cpu_bit@rl
	sub %r3, 20			; *delay*

;----------------------------------------------------------------------------

;#macro SET_b_A $1, $2
;	xoor %A, %A, 1<<$2		; %A = A|(1<<b)
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_SET_0_A:
	or	%r0,0x1		; 	xoor %r0, %r0, 0x1		; %A = A|(1<<b)	; 	SET_b_A CYCLE_SET_0_A, 0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_1_A:
	or	%r0,0x2		; 	xoor %r0, %r0, 0x2		; %A = A|(1<<b)	; 	SET_b_A CYCLE_SET_1_A, 1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_2_A:
	or	%r0,0x4		; 	xoor %r0, %r0, 0x4		; %A = A|(1<<b)	; 	SET_b_A CYCLE_SET_2_A, 2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_3_A:
	or	%r0,0x8		; 	xoor %r0, %r0, 0x8		; %A = A|(1<<b)	; 	SET_b_A CYCLE_SET_3_A, 3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_4_A:
	or	%r0,0x10	; 	xoor %r0, %r0, 0x10		; %A = A|(1<<b)	; 	SET_b_A CYCLE_SET_4_A, 4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_5_A:
	ext	0x0		; 	xoor %r0, %r0, 0x20		; %A = A|(1<<b)	; 	SET_b_A CYCLE_SET_5_A, 5
	or	%r0,0x20
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_6_A:
	ext	0x1		; 	xoor %r0, %r0, 0x40		; %A = A|(1<<b)	; 	SET_b_A CYCLE_SET_6_A, 6
	or	%r0,0x0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_7_A:
	ext	0x2		; 	xoor %r0, %r0, 0x80		; %A = A|(1<<b)	; 	SET_b_A CYCLE_SET_7_A, 7
	or	%r0,0x0
	ret.d
	sub %r3, 8			; *delay*

;#macro SET_b_r $1, $2, $3
;	xbset [%CPU+$3], $2		; r = r|(1<<b)
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_SET_0_B:
	ext	0x3		; 	xbset [%r4+0x3], 0x0		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_0_B, 0, B
	bset	[%r4],0x0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_1_B:
	ext	0x3		; 	xbset [%r4+0x3], 0x1		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_1_B, 1, B
	bset	[%r4],0x1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_2_B:
	ext	0x3		; 	xbset [%r4+0x3], 0x2		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_2_B, 2, B
	bset	[%r4],0x2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_3_B:
	ext	0x3		; 	xbset [%r4+0x3], 0x3		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_3_B, 3, B
	bset	[%r4],0x3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_4_B:
	ext	0x3		; 	xbset [%r4+0x3], 0x4		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_4_B, 4, B
	bset	[%r4],0x4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_5_B:
	ext	0x3		; 	xbset [%r4+0x3], 0x5		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_5_B, 5, B
	bset	[%r4],0x5
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_6_B:
	ext	0x3		; 	xbset [%r4+0x3], 0x6		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_6_B, 6, B
	bset	[%r4],0x6
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_7_B:
	ext	0x3		; 	xbset [%r4+0x3], 0x7		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_7_B, 7, B
	bset	[%r4],0x7
	ret.d
	sub %r3, 8			; *delay*

z80cpu_SET_0_C:
	ext	0x2		; 	xbset [%r4+0x2], 0x0		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_0_C, 0, C
	bset	[%r4],0x0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_1_C:
	ext	0x2		; 	xbset [%r4+0x2], 0x1		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_1_C, 1, C
	bset	[%r4],0x1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_2_C:
	ext	0x2		; 	xbset [%r4+0x2], 0x2		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_2_C, 2, C
	bset	[%r4],0x2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_3_C:
	ext	0x2		; 	xbset [%r4+0x2], 0x3		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_3_C, 3, C
	bset	[%r4],0x3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_4_C:
	ext	0x2		; 	xbset [%r4+0x2], 0x4		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_4_C, 4, C
	bset	[%r4],0x4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_5_C:
	ext	0x2		; 	xbset [%r4+0x2], 0x5		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_5_C, 5, C
	bset	[%r4],0x5
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_6_C:
	ext	0x2		; 	xbset [%r4+0x2], 0x6		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_6_C, 6, C
	bset	[%r4],0x6
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_7_C:
	ext	0x2		; 	xbset [%r4+0x2], 0x7		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_7_C, 7, C
	bset	[%r4],0x7
	ret.d
	sub %r3, 8			; *delay*

z80cpu_SET_0_D:
	ext	0x5		; 	xbset [%r4+0x5], 0x0		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_0_D, 0, D
	bset	[%r4],0x0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_1_D:
	ext	0x5		; 	xbset [%r4+0x5], 0x1		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_1_D, 1, D
	bset	[%r4],0x1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_2_D:
	ext	0x5		; 	xbset [%r4+0x5], 0x2		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_2_D, 2, D
	bset	[%r4],0x2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_3_D:
	ext	0x5		; 	xbset [%r4+0x5], 0x3		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_3_D, 3, D
	bset	[%r4],0x3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_4_D:
	ext	0x5		; 	xbset [%r4+0x5], 0x4		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_4_D, 4, D
	bset	[%r4],0x4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_5_D:
	ext	0x5		; 	xbset [%r4+0x5], 0x5		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_5_D, 5, D
	bset	[%r4],0x5
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_6_D:
	ext	0x5		; 	xbset [%r4+0x5], 0x6		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_6_D, 6, D
	bset	[%r4],0x6
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_7_D:
	ext	0x5		; 	xbset [%r4+0x5], 0x7		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_7_D, 7, D
	bset	[%r4],0x7
	ret.d
	sub %r3, 8			; *delay*

z80cpu_SET_0_E:
	ext	0x4		; 	xbset [%r4+0x4], 0x0		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_0_E, 0, E
	bset	[%r4],0x0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_1_E:
	ext	0x4		; 	xbset [%r4+0x4], 0x1		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_1_E, 1, E
	bset	[%r4],0x1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_2_E:
	ext	0x4		; 	xbset [%r4+0x4], 0x2		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_2_E, 2, E
	bset	[%r4],0x2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_3_E:
	ext	0x4		; 	xbset [%r4+0x4], 0x3		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_3_E, 3, E
	bset	[%r4],0x3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_4_E:
	ext	0x4		; 	xbset [%r4+0x4], 0x4		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_4_E, 4, E
	bset	[%r4],0x4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_5_E:
	ext	0x4		; 	xbset [%r4+0x4], 0x5		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_5_E, 5, E
	bset	[%r4],0x5
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_6_E:
	ext	0x4		; 	xbset [%r4+0x4], 0x6		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_6_E, 6, E
	bset	[%r4],0x6
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_7_E:
	ext	0x4		; 	xbset [%r4+0x4], 0x7		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_7_E, 7, E
	bset	[%r4],0x7
	ret.d
	sub %r3, 8			; *delay*

z80cpu_SET_0_H:
	ext	0x7		; 	xbset [%r4+0x7], 0x0		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_0_H, 0, H
	bset	[%r4],0x0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_1_H:
	ext	0x7		; 	xbset [%r4+0x7], 0x1		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_1_H, 1, H
	bset	[%r4],0x1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_2_H:
	ext	0x7		; 	xbset [%r4+0x7], 0x2		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_2_H, 2, H
	bset	[%r4],0x2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_3_H:
	ext	0x7		; 	xbset [%r4+0x7], 0x3		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_3_H, 3, H
	bset	[%r4],0x3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_4_H:
	ext	0x7		; 	xbset [%r4+0x7], 0x4		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_4_H, 4, H
	bset	[%r4],0x4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_5_H:
	ext	0x7		; 	xbset [%r4+0x7], 0x5		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_5_H, 5, H
	bset	[%r4],0x5
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_6_H:
	ext	0x7		; 	xbset [%r4+0x7], 0x6		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_6_H, 6, H
	bset	[%r4],0x6
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_7_H:
	ext	0x7		; 	xbset [%r4+0x7], 0x7		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_7_H, 7, H
	bset	[%r4],0x7
	ret.d
	sub %r3, 8			; *delay*

z80cpu_SET_0_L:
	ext	0x6		; 	xbset [%r4+0x6], 0x0		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_0_L, 0, L
	bset	[%r4],0x0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_1_L:
	ext	0x6		; 	xbset [%r4+0x6], 0x1		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_1_L, 1, L
	bset	[%r4],0x1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_2_L:
	ext	0x6		; 	xbset [%r4+0x6], 0x2		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_2_L, 2, L
	bset	[%r4],0x2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_3_L:
	ext	0x6		; 	xbset [%r4+0x6], 0x3		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_3_L, 3, L
	bset	[%r4],0x3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_4_L:
	ext	0x6		; 	xbset [%r4+0x6], 0x4		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_4_L, 4, L
	bset	[%r4],0x4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_5_L:
	ext	0x6		; 	xbset [%r4+0x6], 0x5		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_5_L, 5, L
	bset	[%r4],0x5
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_6_L:
	ext	0x6		; 	xbset [%r4+0x6], 0x6		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_6_L, 6, L
	bset	[%r4],0x6
	ret.d
	sub %r3, 8			; *delay*
z80cpu_SET_7_L:
	ext	0x6		; 	xbset [%r4+0x6], 0x7		; r = r|(1<<b)	; 	SET_b_r CYCLE_SET_7_L, 7, L
	bset	[%r4],0x7
	ret.d
	sub %r3, 8			; *delay*

;#macro SET_b_IHLI $1, $2
;	xld.uh %t0, [%CPU+HL]		; %t0 = HL
;	add    %t0, %MEM		; %t0 = mem+HL
;	bset  [%t0], $2			; [mem+HL] = [mem+HL]|(1<<b)
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_SET_0_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	SET_b_IHLI CYCLE_SET_0_IHLI, 0
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bset  [%r12], 0			; [mem+HL] = [mem+HL]|(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_SET_1_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	SET_b_IHLI CYCLE_SET_1_IHLI, 1
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bset  [%r12], 1			; [mem+HL] = [mem+HL]|(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_SET_2_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	SET_b_IHLI CYCLE_SET_2_IHLI, 2
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bset  [%r12], 2			; [mem+HL] = [mem+HL]|(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_SET_3_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	SET_b_IHLI CYCLE_SET_3_IHLI, 3
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bset  [%r12], 3			; [mem+HL] = [mem+HL]|(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_SET_4_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	SET_b_IHLI CYCLE_SET_4_IHLI, 4
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bset  [%r12], 4			; [mem+HL] = [mem+HL]|(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_SET_5_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	SET_b_IHLI CYCLE_SET_5_IHLI, 5
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bset  [%r12], 5			; [mem+HL] = [mem+HL]|(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_SET_6_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	SET_b_IHLI CYCLE_SET_6_IHLI, 6
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bset  [%r12], 6			; [mem+HL] = [mem+HL]|(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_SET_7_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	SET_b_IHLI CYCLE_SET_7_IHLI, 7
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bset  [%r12], 7			; [mem+HL] = [mem+HL]|(1<<b)
	ret.d
	sub %r3, 15			; *delay*

;#macro SET_b_IaddrI $1, $2
;	bset [%s0], $2			; [addr] = [addr]|(1<<b)
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_SET_0_IaddrI:
	bset [%r6], 0			; [addr] = [addr]|(1<<b)	; 	SET_b_IaddrI CYCLE_SET_0_IaddrI, 0
	ret.d
	sub %r3, 23			; *delay*
z80cpu_SET_1_IaddrI:
	bset [%r6], 1			; [addr] = [addr]|(1<<b)	; 	SET_b_IaddrI CYCLE_SET_1_IaddrI, 1
	ret.d
	sub %r3, 23			; *delay*
z80cpu_SET_2_IaddrI:
	bset [%r6], 2			; [addr] = [addr]|(1<<b)	; 	SET_b_IaddrI CYCLE_SET_2_IaddrI, 2
	ret.d
	sub %r3, 23			; *delay*
z80cpu_SET_3_IaddrI:
	bset [%r6], 3			; [addr] = [addr]|(1<<b)	; 	SET_b_IaddrI CYCLE_SET_3_IaddrI, 3
	ret.d
	sub %r3, 23			; *delay*
z80cpu_SET_4_IaddrI:
	bset [%r6], 4			; [addr] = [addr]|(1<<b)	; 	SET_b_IaddrI CYCLE_SET_4_IaddrI, 4
	ret.d
	sub %r3, 23			; *delay*
z80cpu_SET_5_IaddrI:
	bset [%r6], 5			; [addr] = [addr]|(1<<b)	; 	SET_b_IaddrI CYCLE_SET_5_IaddrI, 5
	ret.d
	sub %r3, 23			; *delay*
z80cpu_SET_6_IaddrI:
	bset [%r6], 6			; [addr] = [addr]|(1<<b)	; 	SET_b_IaddrI CYCLE_SET_6_IaddrI, 6
	ret.d
	sub %r3, 23			; *delay*
z80cpu_SET_7_IaddrI:
	bset [%r6], 7			; [addr] = [addr]|(1<<b)	; 	SET_b_IaddrI CYCLE_SET_7_IaddrI, 7
	ret.d
	sub %r3, 23			; *delay*

;----------------------------------------------------------------------------

;#macro RES_b_A $1, $2
;	xand %A, %A, ~(1<<$2)		; %A = A&~(1<<b)
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_RES_0_A:
	and	%r0,0x3e	; 	xand %r0, %r0, -2		; %A = A&~(1<<b)	; 	RES_b_A CYCLE_RES_0_A, 0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_1_A:
	and	%r0,0x3d	; 	xand %r0, %r0, -3		; %A = A&~(1<<b)	; 	RES_b_A CYCLE_RES_1_A, 1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_2_A:
	and	%r0,0x3b	; 	xand %r0, %r0, -5		; %A = A&~(1<<b)	; 	RES_b_A CYCLE_RES_2_A, 2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_3_A:
	and	%r0,0x37	; 	xand %r0, %r0, -9		; %A = A&~(1<<b)	; 	RES_b_A CYCLE_RES_3_A, 3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_4_A:
	and	%r0,0x2f	; 	xand %r0, %r0, -17		; %A = A&~(1<<b)	; 	RES_b_A CYCLE_RES_4_A, 4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_5_A:
	ext	0x1fff		; 	xand %r0, %r0, -33		; %A = A&~(1<<b)	; 	RES_b_A CYCLE_RES_5_A, 5
	and	%r0,0x1f
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_6_A:
	ext	0x1ffe		; 	xand %r0, %r0, -65		; %A = A&~(1<<b)	; 	RES_b_A CYCLE_RES_6_A, 6
	and	%r0,0x3f
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_7_A:
	ext	0x1ffd		; 	xand %r0, %r0, -129		; %A = A&~(1<<b)	; 	RES_b_A CYCLE_RES_7_A, 7
	and	%r0,0x3f
	ret.d
	sub %r3, 8			; *delay*

;#macro RES_b_r $1, $2, $3
;	xbclr [%CPU+$3], $2		; r = r&~(1<<b)
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_RES_0_B:
	ext	0x3		; 	xbclr [%r4+0x3], 0x0		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_0_B, 0, B
	bclr	[%r4],0x0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_1_B:
	ext	0x3		; 	xbclr [%r4+0x3], 0x1		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_1_B, 1, B
	bclr	[%r4],0x1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_2_B:
	ext	0x3		; 	xbclr [%r4+0x3], 0x2		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_2_B, 2, B
	bclr	[%r4],0x2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_3_B:
	ext	0x3		; 	xbclr [%r4+0x3], 0x3		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_3_B, 3, B
	bclr	[%r4],0x3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_4_B:
	ext	0x3		; 	xbclr [%r4+0x3], 0x4		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_4_B, 4, B
	bclr	[%r4],0x4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_5_B:
	ext	0x3		; 	xbclr [%r4+0x3], 0x5		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_5_B, 5, B
	bclr	[%r4],0x5
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_6_B:
	ext	0x3		; 	xbclr [%r4+0x3], 0x6		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_6_B, 6, B
	bclr	[%r4],0x6
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_7_B:
	ext	0x3		; 	xbclr [%r4+0x3], 0x7		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_7_B, 7, B
	bclr	[%r4],0x7
	ret.d
	sub %r3, 8			; *delay*

z80cpu_RES_0_C:
	ext	0x2		; 	xbclr [%r4+0x2], 0x0		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_0_C, 0, C
	bclr	[%r4],0x0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_1_C:
	ext	0x2		; 	xbclr [%r4+0x2], 0x1		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_1_C, 1, C
	bclr	[%r4],0x1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_2_C:
	ext	0x2		; 	xbclr [%r4+0x2], 0x2		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_2_C, 2, C
	bclr	[%r4],0x2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_3_C:
	ext	0x2		; 	xbclr [%r4+0x2], 0x3		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_3_C, 3, C
	bclr	[%r4],0x3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_4_C:
	ext	0x2		; 	xbclr [%r4+0x2], 0x4		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_4_C, 4, C
	bclr	[%r4],0x4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_5_C:
	ext	0x2		; 	xbclr [%r4+0x2], 0x5		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_5_C, 5, C
	bclr	[%r4],0x5
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_6_C:
	ext	0x2		; 	xbclr [%r4+0x2], 0x6		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_6_C, 6, C
	bclr	[%r4],0x6
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_7_C:
	ext	0x2		; 	xbclr [%r4+0x2], 0x7		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_7_C, 7, C
	bclr	[%r4],0x7
	ret.d
	sub %r3, 8			; *delay*

z80cpu_RES_0_D:
	ext	0x5		; 	xbclr [%r4+0x5], 0x0		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_0_D, 0, D
	bclr	[%r4],0x0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_1_D:
	ext	0x5		; 	xbclr [%r4+0x5], 0x1		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_1_D, 1, D
	bclr	[%r4],0x1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_2_D:
	ext	0x5		; 	xbclr [%r4+0x5], 0x2		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_2_D, 2, D
	bclr	[%r4],0x2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_3_D:
	ext	0x5		; 	xbclr [%r4+0x5], 0x3		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_3_D, 3, D
	bclr	[%r4],0x3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_4_D:
	ext	0x5		; 	xbclr [%r4+0x5], 0x4		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_4_D, 4, D
	bclr	[%r4],0x4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_5_D:
	ext	0x5		; 	xbclr [%r4+0x5], 0x5		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_5_D, 5, D
	bclr	[%r4],0x5
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_6_D:
	ext	0x5		; 	xbclr [%r4+0x5], 0x6		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_6_D, 6, D
	bclr	[%r4],0x6
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_7_D:
	ext	0x5		; 	xbclr [%r4+0x5], 0x7		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_7_D, 7, D
	bclr	[%r4],0x7
	ret.d
	sub %r3, 8			; *delay*

z80cpu_RES_0_E:
	ext	0x4		; 	xbclr [%r4+0x4], 0x0		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_0_E, 0, E
	bclr	[%r4],0x0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_1_E:
	ext	0x4		; 	xbclr [%r4+0x4], 0x1		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_1_E, 1, E
	bclr	[%r4],0x1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_2_E:
	ext	0x4		; 	xbclr [%r4+0x4], 0x2		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_2_E, 2, E
	bclr	[%r4],0x2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_3_E:
	ext	0x4		; 	xbclr [%r4+0x4], 0x3		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_3_E, 3, E
	bclr	[%r4],0x3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_4_E:
	ext	0x4		; 	xbclr [%r4+0x4], 0x4		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_4_E, 4, E
	bclr	[%r4],0x4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_5_E:
	ext	0x4		; 	xbclr [%r4+0x4], 0x5		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_5_E, 5, E
	bclr	[%r4],0x5
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_6_E:
	ext	0x4		; 	xbclr [%r4+0x4], 0x6		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_6_E, 6, E
	bclr	[%r4],0x6
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_7_E:
	ext	0x4		; 	xbclr [%r4+0x4], 0x7		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_7_E, 7, E
	bclr	[%r4],0x7
	ret.d
	sub %r3, 8			; *delay*

z80cpu_RES_0_H:
	ext	0x7		; 	xbclr [%r4+0x7], 0x0		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_0_H, 0, H
	bclr	[%r4],0x0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_1_H:
	ext	0x7		; 	xbclr [%r4+0x7], 0x1		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_1_H, 1, H
	bclr	[%r4],0x1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_2_H:
	ext	0x7		; 	xbclr [%r4+0x7], 0x2		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_2_H, 2, H
	bclr	[%r4],0x2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_3_H:
	ext	0x7		; 	xbclr [%r4+0x7], 0x3		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_3_H, 3, H
	bclr	[%r4],0x3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_4_H:
	ext	0x7		; 	xbclr [%r4+0x7], 0x4		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_4_H, 4, H
	bclr	[%r4],0x4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_5_H:
	ext	0x7		; 	xbclr [%r4+0x7], 0x5		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_5_H, 5, H
	bclr	[%r4],0x5
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_6_H:
	ext	0x7		; 	xbclr [%r4+0x7], 0x6		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_6_H, 6, H
	bclr	[%r4],0x6
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_7_H:
	ext	0x7		; 	xbclr [%r4+0x7], 0x7		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_7_H, 7, H
	bclr	[%r4],0x7
	ret.d
	sub %r3, 8			; *delay*

z80cpu_RES_0_L:
	ext	0x6		; 	xbclr [%r4+0x6], 0x0		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_0_L, 0, L
	bclr	[%r4],0x0
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_1_L:
	ext	0x6		; 	xbclr [%r4+0x6], 0x1		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_1_L, 1, L
	bclr	[%r4],0x1
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_2_L:
	ext	0x6		; 	xbclr [%r4+0x6], 0x2		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_2_L, 2, L
	bclr	[%r4],0x2
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_3_L:
	ext	0x6		; 	xbclr [%r4+0x6], 0x3		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_3_L, 3, L
	bclr	[%r4],0x3
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_4_L:
	ext	0x6		; 	xbclr [%r4+0x6], 0x4		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_4_L, 4, L
	bclr	[%r4],0x4
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_5_L:
	ext	0x6		; 	xbclr [%r4+0x6], 0x5		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_5_L, 5, L
	bclr	[%r4],0x5
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_6_L:
	ext	0x6		; 	xbclr [%r4+0x6], 0x6		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_6_L, 6, L
	bclr	[%r4],0x6
	ret.d
	sub %r3, 8			; *delay*
z80cpu_RES_7_L:
	ext	0x6		; 	xbclr [%r4+0x6], 0x7		; r = r&~(1<<b)	; 	RES_b_r CYCLE_RES_7_L, 7, L
	bclr	[%r4],0x7
	ret.d
	sub %r3, 8			; *delay*

;#macro RES_b_IHLI $1, $2
;	xld.uh %t0, [%CPU+HL]		; %t0 = HL
;	add    %t0, %MEM		; %t0 = mem+HL
;	bclr  [%t0], $2			; [mem+HL] = [mem+HL]&~(1<<b)
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_RES_0_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	RES_b_IHLI CYCLE_RES_0_IHLI, 0
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bclr  [%r12], 0			; [mem+HL] = [mem+HL]&~(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_RES_1_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	RES_b_IHLI CYCLE_RES_1_IHLI, 1
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bclr  [%r12], 1			; [mem+HL] = [mem+HL]&~(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_RES_2_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	RES_b_IHLI CYCLE_RES_2_IHLI, 2
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bclr  [%r12], 2			; [mem+HL] = [mem+HL]&~(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_RES_3_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	RES_b_IHLI CYCLE_RES_3_IHLI, 3
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bclr  [%r12], 3			; [mem+HL] = [mem+HL]&~(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_RES_4_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	RES_b_IHLI CYCLE_RES_4_IHLI, 4
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bclr  [%r12], 4			; [mem+HL] = [mem+HL]&~(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_RES_5_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	RES_b_IHLI CYCLE_RES_5_IHLI, 5
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bclr  [%r12], 5			; [mem+HL] = [mem+HL]&~(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_RES_6_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	RES_b_IHLI CYCLE_RES_6_IHLI, 6
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bclr  [%r12], 6			; [mem+HL] = [mem+HL]&~(1<<b)
	ret.d
	sub %r3, 15			; *delay*
z80cpu_RES_7_IHLI:
	ext	0x6		; 	xld.uh %r12, [%r4+0x6]		; %t0 = HL	; 	RES_b_IHLI CYCLE_RES_7_IHLI, 7
	ld.uh	%r12,[%r4]
	add    %r12, %r5		; %t0 = mem+HL
	bclr  [%r12], 7			; [mem+HL] = [mem+HL]&~(1<<b)
	ret.d
	sub %r3, 15			; *delay*

;#macro RES_b_IaddrI $1, $2
;	bclr [%s0], $2			; [addr] = [addr]&~(1<<b)
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_RES_0_IaddrI:
	bclr [%r6], 0			; [addr] = [addr]&~(1<<b)	; 	RES_b_IaddrI CYCLE_RES_0_IaddrI, 0
	ret.d
	sub %r3, 23			; *delay*
z80cpu_RES_1_IaddrI:
	bclr [%r6], 1			; [addr] = [addr]&~(1<<b)	; 	RES_b_IaddrI CYCLE_RES_1_IaddrI, 1
	ret.d
	sub %r3, 23			; *delay*
z80cpu_RES_2_IaddrI:
	bclr [%r6], 2			; [addr] = [addr]&~(1<<b)	; 	RES_b_IaddrI CYCLE_RES_2_IaddrI, 2
	ret.d
	sub %r3, 23			; *delay*
z80cpu_RES_3_IaddrI:
	bclr [%r6], 3			; [addr] = [addr]&~(1<<b)	; 	RES_b_IaddrI CYCLE_RES_3_IaddrI, 3
	ret.d
	sub %r3, 23			; *delay*
z80cpu_RES_4_IaddrI:
	bclr [%r6], 4			; [addr] = [addr]&~(1<<b)	; 	RES_b_IaddrI CYCLE_RES_4_IaddrI, 4
	ret.d
	sub %r3, 23			; *delay*
z80cpu_RES_5_IaddrI:
	bclr [%r6], 5			; [addr] = [addr]&~(1<<b)	; 	RES_b_IaddrI CYCLE_RES_5_IaddrI, 5
	ret.d
	sub %r3, 23			; *delay*
z80cpu_RES_6_IaddrI:
	bclr [%r6], 6			; [addr] = [addr]&~(1<<b)	; 	RES_b_IaddrI CYCLE_RES_6_IaddrI, 6
	ret.d
	sub %r3, 23			; *delay*
z80cpu_RES_7_IaddrI:
	bclr [%r6], 7			; [addr] = [addr]&~(1<<b)	; 	RES_b_IaddrI CYCLE_RES_7_IaddrI, 7
	ret.d
	sub %r3, 23			; *delay*

;****************************************************************************
;	Jump Group
;****************************************************************************

	.global z80cpu_JP_IHLI
	.global z80cpu_JP_IIXI
	.global z80cpu_JP_IIYI

	.global z80cpu_JP_lm
	.global z80cpu_JP_Z_lm
	.global z80cpu_JP_NZ_lm
	.global z80cpu_JP_C_lm
	.global z80cpu_JP_NC_lm
	.global z80cpu_JP_PE_lm
	.global z80cpu_JP_PO_lm
	.global z80cpu_JP_M_lm
	.global z80cpu_JP_P_lm

	.global z80cpu_JR_e
	.global z80cpu_JR_Z_e
	.global z80cpu_JR_NZ_e
	.global z80cpu_JR_C_e
	.global z80cpu_JR_NC_e

	.global z80cpu_DJNZ_e

;----------------------------------------------------------------------------

;#macro JP_IrrI $1, $2
;	xld.uh %PC, [%CPU+$2]		; %PC = rr
;	add    %PC, %MEM		; %PC = mem+rr
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_JP_IHLI:
	ext	0x6		; 	xld.uh %r2, [%r4+0x6]		; %PC = rr	; 	JP_IrrI CYCLE_JP_IHLI, HL
	ld.uh	%r2,[%r4]
	add    %r2, %r5		; %PC = mem+rr
	ret.d
	sub %r3, 4			; *delay*
z80cpu_JP_IIXI:
	ext	0x10		; 	xld.uh %r2, [%r4+0x10]		; %PC = rr	; 	JP_IrrI CYCLE_JP_IIXI, IX
	ld.uh	%r2,[%r4]
	add    %r2, %r5		; %PC = mem+rr
	ret.d
	sub %r3, 8			; *delay*
z80cpu_JP_IIYI:
	ext	0x12		; 	xld.uh %r2, [%r4+0x12]		; %PC = rr	; 	JP_IrrI CYCLE_JP_IIYI, IY
	ld.uh	%r2,[%r4]
	add    %r2, %r5		; %PC = mem+rr
	ret.d
	sub %r3, 8			; *delay*

;----------------------------------------------------------------------------

;
; [note]
;	* PCをロードするときに、
;		ld.ub %t0, [%PC]+	; %t0 = m
;		ld.ub %PC, [%PC]+	; %PC = l
;	 としないよう注意してください。
;	 "ld.ub %PC, [%PC]+"は、読み込んだ値を+1してしまいます。
;	 正しくは、
;		ld.ub %t0, [%PC]+	; %t0 = m
;		ld.ub %PC, [%PC]	; %PC = l
;	 です。
;	 ↓Sun Feb 13 03:00:00 JST 2005 Naoyuki Sawa 追記
;	 再度確認したところ、"ld.ub %PC,[%PC]+"は読み込んだ値を+1するのではなく、
;	 もともとの%PCの値+1が結果となるようです。
;	 たとえば、
;		ld.ub %r10,memory
;		ld.ub %r10,[%r10]+
;	 というコードを実行したあとの%r10の値は、memory+1となり、
;	 [memory]から読み込んだメモリの内容は破棄されてしまうようです。
;	 CPUの内部では、次のような処理が行われているものと推測します。
;		tmp = %rs(=%r10)
;		%rd(=%r10) = [tmp]
;		%rs(=%r10) = tmp + 1
;	 同様に、ハーフワードサイズの読み込みを行った場合の%r10の値はmemory+2、
;	 ワードサイズの読み込みを行った場合の%r10の値は%memory+4となりました。
;	 コードや読み込み先データの位置をSRAMおよび高速RAMに配置換えしたり、
;	 24MHzと48MHzモードを確認したところ、すべて以上の結果となりました。
;	 "ld.ub %PC,[%PC]+"の振る舞いを、明示的に使う利点は無いと思います。
;	 オートインクリメントメモリアクセスでは、転送元・転送先に同じレジスタを
;	 ★絶対に★指定しないよう、注意してください。
;
z80cpu_JP_lm:
	ld.ub %r12, [%r2]+		; %t0 = m
	ld.ub %r2, [%r2]		; %PC = l
	sll	%r2,0x8		; 	xsll  %r2, 8			; %PC = lm
	or    %r2, %r12
	add   %r2, %r5			; %PC = mem+lm
	ret.d
	sub %r3, 10	; *delay*

;
; [note]
;	* 条件成立/不成立にかかわらず、JP c lmの消費サイクル数はJP lmと同じです。
;	  条件成立時は、JP lmの末尾にてCycleを減らします。
;	  条件不成立時は、JP c lmの末尾にてCycleを減らします。
;
;#macro JP_c_lm $1, $2
;	xand %r9, %F, $2		; if F($2) then
;	xjrne z80cpu_JP_lm		;   JP lm
;	xadd %PC, %PC, 2		; else skip lm
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_JP_Z_lm:
	ext	0x2		; 	xand %r9, %r1, 0x02		; if F($2) then	; 	JP_c_lm CYCLE_JP_Z_lm , ZF
	and	%r9,%r1
	jrne	z80cpu_JP_lm	; 	xjrne z80cpu_JP_lm		;   JP lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*
z80cpu_JP_C_lm:
	ext	0x8		; 	xand %r9, %r1, 0x08		; if F($2) then	; 	JP_c_lm CYCLE_JP_C_lm , CF
	and	%r9,%r1
	jrne	z80cpu_JP_lm	; 	xjrne z80cpu_JP_lm		;   JP lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*
z80cpu_JP_PE_lm:
	ext	0x4		; 	xand %r9, %r1, 0x04		; if F($2) then	; 	JP_c_lm CYCLE_JP_PE_lm, PF
	and	%r9,%r1
	jrne	z80cpu_JP_lm	; 	xjrne z80cpu_JP_lm		;   JP lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*
z80cpu_JP_M_lm:
	ext	0x1		; 	xand %r9, %r1, 0x01		; if F($2) then	; 	JP_c_lm CYCLE_JP_M_lm , SF
	and	%r9,%r1
	jrne	z80cpu_JP_lm	; 	xjrne z80cpu_JP_lm		;   JP lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*

;
; [note]
;	* 条件成立/不成立にかかわらず、JP c lmの消費サイクル数はJP lmと同じです。
;	  条件成立時は、JP lmの末尾にてCycleを減らします。
;	  条件不成立時は、JP c lmの末尾にてCycleを減らします。
;
;#macro JP_Nc_lm $1, $2
;	xand %r9, %F, $2		; if !F($2) then
;	xjreq z80cpu_JP_lm		;   JP lm
;	xadd %PC, %PC, 2		; else skip lm
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_JP_NZ_lm:
	ext	0x2		; 	xand %r9, %r1, 0x02		; if !F($2) then	; 	JP_Nc_lm CYCLE_JP_NZ_lm, ZF
	and	%r9,%r1
	jreq	z80cpu_JP_lm	; 	xjreq z80cpu_JP_lm		;   JP lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*
z80cpu_JP_NC_lm:
	ext	0x8		; 	xand %r9, %r1, 0x08		; if !F($2) then	; 	JP_Nc_lm CYCLE_JP_NC_lm, CF
	and	%r9,%r1
	jreq	z80cpu_JP_lm	; 	xjreq z80cpu_JP_lm		;   JP lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*
z80cpu_JP_PO_lm:
	ext	0x4		; 	xand %r9, %r1, 0x04		; if !F($2) then	; 	JP_Nc_lm CYCLE_JP_PO_lm, PF
	and	%r9,%r1
	jreq	z80cpu_JP_lm	; 	xjreq z80cpu_JP_lm		;   JP lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*
z80cpu_JP_P_lm:
	ext	0x1		; 	xand %r9, %r1, 0x01		; if !F($2) then	; 	JP_Nc_lm CYCLE_JP_P_lm , SF
	and	%r9,%r1
	jreq	z80cpu_JP_lm	; 	xjreq z80cpu_JP_lm		;   JP lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*

;----------------------------------------------------------------------------

z80cpu_JR_e:
	ld.b %r12, [%r2]+		; %t0 = e (signed)
	add  %r2, %r12			; %PC = PC+e
	ret.d
	sub %r3, 12		; *delay*

;
; [note]
;	* 条件成立時は、JR c eの消費サイクル数はJR eと同じです。
;	  条件成立時は、JR eの末尾にてCycleを減らします。
;	* 条件不成立時は、JR c eの消費サイクル数はJR eと異なります。
;	  条件不成立時は、JR c eの末尾にてCycleを減らします。
;
;#macro JR_c_e $1, $2
;	xand %r9, %F, $2		; if F($2) then
;	xjrne z80cpu_JR_e		;   JR e
;	xadd %PC, %PC, 1		; else skip e
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

;
; [note]
;	* 条件成立時は、JR c eの消費サイクル数はJR eと同じです。
;	  条件成立時は、JR eの末尾にてCycleを減らします。
;	* 条件不成立時は、JR c eの消費サイクル数はJR eと異なります。
;	  条件不成立時は、JR c eの末尾にてCycleを減らします。
;
z80cpu_JR_Z_e:
	ext	0x2		; 	xand %r9, %r1, 0x02		; if F($2) then	; 	JR_c_e CYCLE_JR_Z_e, ZF
	and	%r9,%r1
	jrne	z80cpu_JR_e	; 	xjrne z80cpu_JR_e		;   JR e
	add	%r2,0x1		; 	xadd %r2, %r2, 1		; else skip e
	ret.d
	sub %r3, 7			; *delay*
z80cpu_JR_C_e:
	ext	0x8		; 	xand %r9, %r1, 0x08		; if F($2) then	; 	JR_c_e CYCLE_JR_C_e, CF
	and	%r9,%r1
	jrne	z80cpu_JR_e	; 	xjrne z80cpu_JR_e		;   JR e
	add	%r2,0x1		; 	xadd %r2, %r2, 1		; else skip e
	ret.d
	sub %r3, 7			; *delay*

;#macro JR_Nc_e $1, $2
;	xand %r9, %F, $2		; if !F($2) then
;	xjreq z80cpu_JR_e		;   JR e
;	xadd %PC, %PC, 1		; else skip e
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_JR_NZ_e:
	ext	0x2		; 	xand %r9, %r1, 0x02		; if !F($2) then	; 	JR_Nc_e CYCLE_JR_NZ_e, ZF
	and	%r9,%r1
	jreq	z80cpu_JR_e	; 	xjreq z80cpu_JR_e		;   JR e
	add	%r2,0x1		; 	xadd %r2, %r2, 1		; else skip e
	ret.d
	sub %r3, 7			; *delay*
z80cpu_JR_NC_e:
	ext	0x8		; 	xand %r9, %r1, 0x08		; if !F($2) then	; 	JR_Nc_e CYCLE_JR_NC_e, CF
	and	%r9,%r1
	jreq	z80cpu_JR_e	; 	xjreq z80cpu_JR_e		;   JR e
	add	%r2,0x1		; 	xadd %r2, %r2, 1		; else skip e
	ret.d
	sub %r3, 7			; *delay*

;----------------------------------------------------------------------------

;
; [note]
;	* B-1!=0の場合、追加サイクル数=5で、分岐を行います。
;
z80cpu_DJNZ_e:
	ext	0x3		; 	xld.ub %r12, [%r4+0x3]		; %t0 = B
	ld.ub	%r12,[%r4]
	sub	%r12,0x1	; 	xsub   %r12, %r12, 1		; %t0 = B-1
	ext	0x3		; 	xld.b [%r4+0x3], %r12		; B   = B-1
	ld.b	[%r4],%r12
	ld.b   %r12, [%r2]+		; %t0 = e (signed)
	jreq 3				; if B-1!=0 then
	add    %r2, %r12			;   %PC   = PC+e    (skip?)
	sub    %r3, 5		;   Cycle = Cycle-5 (skip?)
	ret.d
	sub %r3, 8	; *delay*

;****************************************************************************
;	Call and Return Group
;****************************************************************************

	.global z80cpu_CALL_lm
	.global z80cpu_CALL_Z_lm
	.global z80cpu_CALL_NZ_lm
	.global z80cpu_CALL_C_lm
	.global z80cpu_CALL_NC_lm
	.global z80cpu_CALL_PE_lm
	.global z80cpu_CALL_PO_lm
	.global z80cpu_CALL_M_lm
	.global z80cpu_CALL_P_lm

	.global z80cpu_RET
	.global z80cpu_RET_Z
	.global z80cpu_RET_NZ
	.global z80cpu_RET_C
	.global z80cpu_RET_NC
	.global z80cpu_RET_PE
	.global z80cpu_RET_PO
	.global z80cpu_RET_M
	.global z80cpu_RET_P

	.global z80cpu_RETI
	.global z80cpu_RETN

	.global z80cpu_RST_00H
	.global z80cpu_RST_08H
	.global z80cpu_RST_10H
	.global z80cpu_RST_18H
	.global z80cpu_RST_20H
	.global z80cpu_RST_28H
	.global z80cpu_RST_30H
	.global z80cpu_RST_38H

;----------------------------------------------------------------------------

z80cpu_CALL_lm:
	ld.w  %r10 , %r2			; %a0 = mem+PC
	ld.ub %r12, [%r10]+		; %t0 = m, %a0 = mem+PC+1
	ld.ub %r2, [%r10]+		; %PC = l, %a0 = mem+PC+2
	sll	%r2,0x8		; 	xsll  %r2, 8			; %PC = lm
	or    %r2, %r12
	add   %r2, %r5			; %PC = mem+lm
	ext	z80cpu_push@rm	; 	xcall.d z80cpu_push		; push  PC+2
	call.d	z80cpu_push@rl
	sub   %r10, %r5			; %a0 = PC+2 *delay*
	ret.d
	sub %r3, 17	; *delay*

;
; [note]
;	* 条件成立時は、CALL c lmの消費サイクル数はCALL lmと同じです。
;	  条件成立時は、CALL lmの末尾にてCycleを減らします。
;	* 条件不成立時は、CALL c lmの消費サイクル数はCALL lmと異なります。
;	  条件不成立時は、CALL c lmの末尾にてCycleを減らします。
;
;#macro CALL_c_lm $1, $2
;	xand %r9, %F, $2		; if F($2) then
;	xjrne z80cpu_CALL_lm		;   CALL lm
;	xadd %PC, %PC, 2		; else skip lm
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_CALL_Z_lm:
	ext	0x2		; 	xand %r9, %r1, 0x02		; if F($2) then	; 	CALL_c_lm CYCLE_CALL_Z_lm , ZF
	and	%r9,%r1
	jrne	z80cpu_CALL_lm	; 	xjrne z80cpu_CALL_lm		;   CALL lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*
z80cpu_CALL_C_lm:
	ext	0x8		; 	xand %r9, %r1, 0x08		; if F($2) then	; 	CALL_c_lm CYCLE_CALL_C_lm , CF
	and	%r9,%r1
	jrne	z80cpu_CALL_lm	; 	xjrne z80cpu_CALL_lm		;   CALL lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*
z80cpu_CALL_PE_lm:
	ext	0x4		; 	xand %r9, %r1, 0x04		; if F($2) then	; 	CALL_c_lm CYCLE_CALL_PE_lm, PF
	and	%r9,%r1
	jrne	z80cpu_CALL_lm	; 	xjrne z80cpu_CALL_lm		;   CALL lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*
z80cpu_CALL_M_lm:
	ext	0x1		; 	xand %r9, %r1, 0x01		; if F($2) then	; 	CALL_c_lm CYCLE_CALL_M_lm , SF
	and	%r9,%r1
	jrne	z80cpu_CALL_lm	; 	xjrne z80cpu_CALL_lm		;   CALL lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*

;
; [note]
;	* 条件成立時は、CALL c lmの消費サイクル数はCALL lmと同じです。
;	  条件成立時は、CALL lmの末尾にてCycleを減らします。
;	* 条件不成立時は、CALL c lmの消費サイクル数はCALL lmと異なります。
;	  条件不成立時は、CALL c lmの末尾にてCycleを減らします。
;
;#macro CALL_Nc_lm $1, $2
;	xand %r9, %F, $2		; if !F($2) then
;	xjreq z80cpu_CALL_lm		;   CALL lm
;	xadd %PC, %PC, 2		; else skip lm
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_CALL_NZ_lm:
	ext	0x2		; 	xand %r9, %r1, 0x02		; if !F($2) then	; 	CALL_Nc_lm CYCLE_CALL_NZ_lm, ZF
	and	%r9,%r1
	jreq	z80cpu_CALL_lm	; 	xjreq z80cpu_CALL_lm		;   CALL lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*
z80cpu_CALL_NC_lm:
	ext	0x8		; 	xand %r9, %r1, 0x08		; if !F($2) then	; 	CALL_Nc_lm CYCLE_CALL_NC_lm, CF
	and	%r9,%r1
	jreq	z80cpu_CALL_lm	; 	xjreq z80cpu_CALL_lm		;   CALL lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*
z80cpu_CALL_PO_lm:
	ext	0x4		; 	xand %r9, %r1, 0x04		; if !F($2) then	; 	CALL_Nc_lm CYCLE_CALL_PO_lm, PF
	and	%r9,%r1
	jreq	z80cpu_CALL_lm	; 	xjreq z80cpu_CALL_lm		;   CALL lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*
z80cpu_CALL_P_lm:
	ext	0x1		; 	xand %r9, %r1, 0x01		; if !F($2) then	; 	CALL_Nc_lm CYCLE_CALL_P_lm , SF
	and	%r9,%r1
	jreq	z80cpu_CALL_lm	; 	xjreq z80cpu_CALL_lm		;   CALL lm
	add	%r2,0x2		; 	xadd %r2, %r2, 2		; else skip lm
	ret.d
	sub %r3, 10			; *delay*

;----------------------------------------------------------------------------

z80cpu_RET_cc:
	sub	%r3,0x1		; 	xsub %r3, %r3, 1		; RET c条件成立時の追加サイクル数=1
z80cpu_RET:
	ext	z80cpu_pop@rm	; 	xcall z80cpu_pop		; %a0 = PC
	call	z80cpu_pop@rl
	add  %r10 , %r5			; %a0 = mem+PC
	ld.w %r2, %r10			; %PC = mem+PC
	ret.d
	sub %r3, 10		; *delay*

;
; [note]
;	* 条件成立時は、RET cの消費サイクル数はRET+1です。
;	  条件成立時は、RETの先頭および末尾にてCycleを減らします。
;	* 条件不成立時は、RET cの消費サイクル数はRETと異なります。
;	  条件不成立時は、RET cの末尾にてCycleを減らします。
;
;#macro RET_c $1, $2
;	xand %r9, %F, $2		; if F($2) then
;	xjrne z80cpu_RET_cc		;   Cycle = Cycle-1, RET
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_RET_Z:
	ext	0x2		; 	xand %r9, %r1, 0x02		; if F($2) then	; 	RET_c CYCLE_RET_Z , ZF
	and	%r9,%r1
	jrne	z80cpu_RET_cc	; 	xjrne z80cpu_RET_cc		;   Cycle = Cycle-1, RET
	ret.d
	sub %r3, 5			; *delay*
z80cpu_RET_C:
	ext	0x8		; 	xand %r9, %r1, 0x08		; if F($2) then	; 	RET_c CYCLE_RET_C , CF
	and	%r9,%r1
	jrne	z80cpu_RET_cc	; 	xjrne z80cpu_RET_cc		;   Cycle = Cycle-1, RET
	ret.d
	sub %r3, 5			; *delay*
z80cpu_RET_PE:
	ext	0x4		; 	xand %r9, %r1, 0x04		; if F($2) then	; 	RET_c CYCLE_RET_PE, PF
	and	%r9,%r1
	jrne	z80cpu_RET_cc	; 	xjrne z80cpu_RET_cc		;   Cycle = Cycle-1, RET
	ret.d
	sub %r3, 5			; *delay*
z80cpu_RET_M:
	ext	0x1		; 	xand %r9, %r1, 0x01		; if F($2) then	; 	RET_c CYCLE_RET_M , SF
	and	%r9,%r1
	jrne	z80cpu_RET_cc	; 	xjrne z80cpu_RET_cc		;   Cycle = Cycle-1, RET
	ret.d
	sub %r3, 5			; *delay*

;
; [note]
;	* 条件成立時は、RET cの消費サイクル数はRET+1です。
;	  条件成立時は、RETの先頭および末尾にてCycleを減らします。
;	* 条件不成立時は、RET cの消費サイクル数はRETと異なります。
;	  条件不成立時は、RET cの末尾にてCycleを減らします。
;
;#macro RET_Nc $1, $2
;	xand %r9, %F, $2		; if !F($2) then
;	xjreq z80cpu_RET_cc		;   Cycle = Cycle-1, RET
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_RET_NZ:
	ext	0x2		; 	xand %r9, %r1, 0x02		; if !F($2) then	; 	RET_Nc CYCLE_RET_NZ, ZF
	and	%r9,%r1
	jreq	z80cpu_RET_cc	; 	xjreq z80cpu_RET_cc		;   Cycle = Cycle-1, RET
	ret.d
	sub %r3, 5			; *delay*
z80cpu_RET_NC:
	ext	0x8		; 	xand %r9, %r1, 0x08		; if !F($2) then	; 	RET_Nc CYCLE_RET_NC, CF
	and	%r9,%r1
	jreq	z80cpu_RET_cc	; 	xjreq z80cpu_RET_cc		;   Cycle = Cycle-1, RET
	ret.d
	sub %r3, 5			; *delay*
z80cpu_RET_PO:
	ext	0x4		; 	xand %r9, %r1, 0x04		; if !F($2) then	; 	RET_Nc CYCLE_RET_PO, PF
	and	%r9,%r1
	jreq	z80cpu_RET_cc	; 	xjreq z80cpu_RET_cc		;   Cycle = Cycle-1, RET
	ret.d
	sub %r3, 5			; *delay*
z80cpu_RET_P:
	ext	0x1		; 	xand %r9, %r1, 0x01		; if !F($2) then	; 	RET_Nc CYCLE_RET_P , SF
	and	%r9,%r1
	jreq	z80cpu_RET_cc	; 	xjreq z80cpu_RET_cc		;   Cycle = Cycle-1, RET
	ret.d
	sub %r3, 5			; *delay*

;----------------------------------------------------------------------------

z80cpu_RETI:
	ext	z80cpu_pop@rm	; 	xcall z80cpu_pop		; %a0 = PC
	call	z80cpu_pop@rl
	add  %r10, %r5			; %a0 = mem+PC
	ld.w %r2, %r10			; %PC = mem+PC
	ext	z80cpu_CHECK_PENDING@rm	; 	xjp.d z80cpu_CHECK_PENDING	; 保留割り込みの実行を検査します。
	jp.d	z80cpu_CHECK_PENDING@rl
	sub %r3, 14		; *delay*

z80cpu_RETN:
	ext	z80cpu_pop@rm	; 	xcall z80cpu_pop		; %a0 = PC
	call	z80cpu_pop@rl
	add    %r10, %r5		; %a0 = mem+PC
	ld.w   %r2, %r10			; %PC = mem+PC
	ext	0x1c		; 	xld.ub %r12, [%r4+0x1c]		; %t0 = IFF2
	ld.ub	%r12,[%r4]
	ext	0x1b		; 	xld.b [%r4+0x1b], %r12		; IFF1 = %t0
	ld.b	[%r4],%r12
	ext	z80cpu_CHECK_PENDING@rm	; 	xjp.d z80cpu_CHECK_PENDING	; 保留割り込みの実行を検査します。
	jp.d	z80cpu_CHECK_PENDING@rl
	sub %r3, 14		; *delay*

;----------------------------------------------------------------------------

;#macro RST_p $1, $2
;	ld.w %a0, %PC			; %a0 = mem+PC
;	xcall.d z80cpu_push		; push  PC
;	sub  %a0, %MEM			; %a0 = PC *delay*
;	xadd %PC, %MEM, $2		; %PC = mem+$2
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_RST_00H:
	ld.w %r10, %r2			; %a0 = mem+PC	; 	RST_p CYCLE_RST_00H, 0x00
	ext	z80cpu_push@rm	; 	xcall.d z80cpu_push		; push  PC
	call.d	z80cpu_push@rl
	sub  %r10, %r5			; %a0 = PC *delay*
	ext	0x0		; 	xadd %r2, %r5, 0x00		; %PC = mem+$2
	add	%r2,%r5
	ret.d
	sub %r3, 11			; *delay*
z80cpu_RST_08H:
	ld.w %r10, %r2			; %a0 = mem+PC	; 	RST_p CYCLE_RST_08H, 0x08
	ext	z80cpu_push@rm	; 	xcall.d z80cpu_push		; push  PC
	call.d	z80cpu_push@rl
	sub  %r10, %r5			; %a0 = PC *delay*
	ext	0x8		; 	xadd %r2, %r5, 0x08		; %PC = mem+$2
	add	%r2,%r5
	ret.d
	sub %r3, 11			; *delay*
z80cpu_RST_10H:
	ld.w %r10, %r2			; %a0 = mem+PC	; 	RST_p CYCLE_RST_10H, 0x10
	ext	z80cpu_push@rm	; 	xcall.d z80cpu_push		; push  PC
	call.d	z80cpu_push@rl
	sub  %r10, %r5			; %a0 = PC *delay*
	ext	0x10		; 	xadd %r2, %r5, 0x10		; %PC = mem+$2
	add	%r2,%r5
	ret.d
	sub %r3, 11			; *delay*
z80cpu_RST_18H:
	ld.w %r10, %r2			; %a0 = mem+PC	; 	RST_p CYCLE_RST_18H, 0x18
	ext	z80cpu_push@rm	; 	xcall.d z80cpu_push		; push  PC
	call.d	z80cpu_push@rl
	sub  %r10, %r5			; %a0 = PC *delay*
	ext	0x18		; 	xadd %r2, %r5, 0x18		; %PC = mem+$2
	add	%r2,%r5
	ret.d
	sub %r3, 11			; *delay*
z80cpu_RST_20H:
	ld.w %r10, %r2			; %a0 = mem+PC	; 	RST_p CYCLE_RST_20H, 0x20
	ext	z80cpu_push@rm	; 	xcall.d z80cpu_push		; push  PC
	call.d	z80cpu_push@rl
	sub  %r10, %r5			; %a0 = PC *delay*
	ext	0x20		; 	xadd %r2, %r5, 0x20		; %PC = mem+$2
	add	%r2,%r5
	ret.d
	sub %r3, 11			; *delay*
z80cpu_RST_28H:
	ld.w %r10, %r2			; %a0 = mem+PC	; 	RST_p CYCLE_RST_28H, 0x28
	ext	z80cpu_push@rm	; 	xcall.d z80cpu_push		; push  PC
	call.d	z80cpu_push@rl
	sub  %r10, %r5			; %a0 = PC *delay*
	ext	0x28		; 	xadd %r2, %r5, 0x28		; %PC = mem+$2
	add	%r2,%r5
	ret.d
	sub %r3, 11			; *delay*
z80cpu_RST_30H:
	ld.w %r10, %r2			; %a0 = mem+PC	; 	RST_p CYCLE_RST_30H, 0x30
	ext	z80cpu_push@rm	; 	xcall.d z80cpu_push		; push  PC
	call.d	z80cpu_push@rl
	sub  %r10, %r5			; %a0 = PC *delay*
	ext	0x30		; 	xadd %r2, %r5, 0x30		; %PC = mem+$2
	add	%r2,%r5
	ret.d
	sub %r3, 11			; *delay*
z80cpu_RST_38H:
	ld.w %r10, %r2			; %a0 = mem+PC	; 	RST_p CYCLE_RST_38H, 0x38
	ext	z80cpu_push@rm	; 	xcall.d z80cpu_push		; push  PC
	call.d	z80cpu_push@rl
	sub  %r10, %r5			; %a0 = PC *delay*
	ext	0x38		; 	xadd %r2, %r5, 0x38		; %PC = mem+$2
	add	%r2,%r5
	ret.d
	sub %r3, 11			; *delay*

;****************************************************************************
;	Input and Output Group
;****************************************************************************

	.global z80cpu_IN_A_ICI
	.global z80cpu_IN_B_ICI
	.global z80cpu_IN_C_ICI
	.global z80cpu_IN_D_ICI
	.global z80cpu_IN_E_ICI
	.global z80cpu_IN_H_ICI
	.global z80cpu_IN_L_ICI
	.global z80cpu_IN_A_InI

	.global z80cpu_INI
	.global z80cpu_INIR
	.global z80cpu_IND
	.global z80cpu_INDR

	.global z80cpu_OUT_ICI_A
	.global z80cpu_OUT_ICI_B
	.global z80cpu_OUT_ICI_C
	.global z80cpu_OUT_ICI_D
	.global z80cpu_OUT_ICI_E
	.global z80cpu_OUT_ICI_H
	.global z80cpu_OUT_ICI_L
	.global z80cpu_OUT_InI_A

	.global z80cpu_OUTI
	.global z80cpu_OTIR
	.global z80cpu_OUTD
	.global z80cpu_OTDR

;----------------------------------------------------------------------------

z80cpu_IN_A_ICI:
	ext	z80cpu_in@rm	; 	xcall z80cpu_in
	call	z80cpu_in@rl
	ld.w %r0, %r10			; %A = IN (C)
	ret.d
	sub %r3, 12	; *delay*

;#macro IN_r_ICI $1, $2
;	xcall z80cpu_in
;	xld.b [%CPU+$2], %a0		; r = IN (C)
;	ret.d
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_IN_B_ICI:
	ext	z80cpu_in@rm	; 	xcall z80cpu_in	; 	IN_r_ICI CYCLE_IN_B_ICI, B
	call	z80cpu_in@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; r = IN (C)
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 12			; *delay*
z80cpu_IN_C_ICI:
	ext	z80cpu_in@rm	; 	xcall z80cpu_in	; 	IN_r_ICI CYCLE_IN_C_ICI, C
	call	z80cpu_in@rl
	ext	0x2		; 	xld.b [%r4+0x2], %r10		; r = IN (C)
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 12			; *delay*
z80cpu_IN_D_ICI:
	ext	z80cpu_in@rm	; 	xcall z80cpu_in	; 	IN_r_ICI CYCLE_IN_D_ICI, D
	call	z80cpu_in@rl
	ext	0x5		; 	xld.b [%r4+0x5], %r10		; r = IN (C)
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 12			; *delay*
z80cpu_IN_E_ICI:
	ext	z80cpu_in@rm	; 	xcall z80cpu_in	; 	IN_r_ICI CYCLE_IN_E_ICI, E
	call	z80cpu_in@rl
	ext	0x4		; 	xld.b [%r4+0x4], %r10		; r = IN (C)
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 12			; *delay*
z80cpu_IN_H_ICI:
	ext	z80cpu_in@rm	; 	xcall z80cpu_in	; 	IN_r_ICI CYCLE_IN_H_ICI, H
	call	z80cpu_in@rl
	ext	0x7		; 	xld.b [%r4+0x7], %r10		; r = IN (C)
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 12			; *delay*
z80cpu_IN_L_ICI:
	ext	z80cpu_in@rm	; 	xcall z80cpu_in	; 	IN_r_ICI CYCLE_IN_L_ICI, L
	call	z80cpu_in@rl
	ext	0x6		; 	xld.b [%r4+0x6], %r10		; r = IN (C)
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 12			; *delay*

;
;	Condition Bits Affected: None
;
; [note]
;	* "IN A,(C)"とはフラグ変化が異なることに注意してください。
;
z80cpu_IN_A_InI:
	ext	0x24		; 	xld.w  %r11, [%r4+0x24]		; %r11 = IN
	ld.w	%r11,[%r4]
	ld.ub  %r12, [%r2]+		; %r12 = n|A<<8
	sll	%r0,0x8		; 	xsll   %r0, 8			; (アドレスバスのbit15-8にはAレジスタの値が出力されます)
	call.d %r11			; %r10 = IN (n|A<<8)
	or     %r12, %r0			; *delay*
	ld.ub  %r0, %r10			; (戻り値のbit31-8をClear。必要です!!)
	ext	z80cpu+0x0@h	; 	xld.w  %r4, z80cpu		; %r4復元
	ext	z80cpu+0x0@m
	ld.w	%r4,z80cpu+0x0@l
	ext	z80mem+0x0@h	; 	xld.w  %r5, z80mem		; %r5復元
	ext	z80mem+0x0@m
	ld.w	%r5,z80mem+0x0@l
	ret.d
	sub %r3, 11	; *delay*

;----------------------------------------------------------------------------

;
;	S	is unknown
;	Z	is set if B-1 is 0, reset otherwise
;	H	is unknown
;	P/V	is unknown
;	N	is set
;	C	is not affected
;
; [note]
;	* フラグ変化は"DEC B"に等価です。
;
z80cpu_INI:
	ext	0x6		; 	xld.uh %r6, [%r4+0x6]		; %s0 = HL
	ld.uh	%r6,[%r4]
	ext	z80cpu_in@rm	; 	xcall.d z80cpu_in		; %a0 = IN (C)
	call.d	z80cpu_in@rl
	add    %r6, %r5		; %s0 = mem+HL *delay*
	ld.b  [%r6]+, %r10		; [mem+HL] = IN (C), %s0 = mem+HL+1
	sub    %r6, %r5		; %s0 = HL+1
	ext	0x6		; 	xld.h [%r4+0x6], %r6		; HL = HL+1
	ld.h	[%r4],%r6
	;
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = B
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8		; %a0 = B-1
	call	z80cpu_dec8@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; B = B-1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 16		; *delay*

;
;	S	is unknown
;	Z	is set
;	H	is unknown
;	P/V	is unknown
;	N	is set
;	C	is not affected
;
; [note]
;	* B-1==0の場合、INIRの消費サイクル数はINIと同じです。
;	  従って、INIRの中でCycleを減らす必要はありません。
;	* B-1!=0の場合、INIRの消費サイクル数はINI+5です。
;	  INIR命令を繰り返すために、自身の2バイト分戻ります。
;
z80cpu_INIR:
	call	z80cpu_INI	; 	xcall z80cpu_INI		; INI
	ext	0x2		; 	xand %r9, %r1, 0x02
	and	%r9,%r1
	jrne 3
	sub  %r2, 2			; (skip?)
	sub  %r3, 5			; (skip?)
	ret

;
;	S	is unknown
;	Z	is set if B-1 is 0, reset otherwise
;	H	is unknown
;	P/V	is unknown
;	N	is set
;	C	is not affected
;
; [note]
;	* フラグ変化は"DEC B"に等価です。
;
z80cpu_IND:
	ext	0x6		; 	xld.uh %r6, [%r4+0x6]		; %s0 = HL
	ld.uh	%r6,[%r4]
	ext	z80cpu_in@rm	; 	xcall.d z80cpu_in		; %a0 = IN (C)
	call.d	z80cpu_in@rl
	add    %r6, %r5		; %s0 = mem+HL *delay*
	ld.b  [%r6], %r10		; [mem+HL] = IN (C)
	sub    %r6, 1			; %s0 = HL-1
	sub    %r6, %r5		; %s0 = HL-1
	ext	0x6		; 	xld.h [%r4+0x6], %r6		; HL = HL-1
	ld.h	[%r4],%r6
	;
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = B
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8		; %a0 = B-1
	call	z80cpu_dec8@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; B = B-1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 16		; *delay*

;
;	S	is unknown
;	Z	is set
;	H	is unknown
;	P/V	is unknown
;	N	is set
;	C	is not affected
;
; [note]
;	* B-1==0の場合、INDRの消費サイクル数はINDと同じです。
;	  従って、INDRの中でCycleを減らす必要はありません。
;	* B-1!=0の場合、INDRの消費サイクル数はIND+5です。
;	  INDR命令を繰り返すために、自身の2バイト分戻ります。
;
z80cpu_INDR:
	call	z80cpu_IND	; 	xcall z80cpu_IND		; IND
	ext	0x2		; 	xand %r9, %r1, 0x02
	and	%r9,%r1
	jrne 3
	sub  %r2, 2			; (skip?)
	sub  %r3, 5			; (skip?)
	ret

;----------------------------------------------------------------------------

;
;	Condition Bits Affected: None
;
z80cpu_OUT_ICI_A:
	ld.w %r10, %r0			; %a0 = A
	ext	z80cpu_out@rm	; 	xjp.d z80cpu_out
	jp.d	z80cpu_out@rl
	sub %r3, 12	; *delay*

;
;	Condition Bits Affected: None
;
;#macro OUT_ICI_r $1, $2
;	xld.ub %a0, [%CPU+$2]		; %a0 = r
;	xjp.d z80cpu_out
;	sub %CYCLE, $1			; *delay*
;#endm

z80cpu_OUT_ICI_B:
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = r	; 	OUT_ICI_r CYCLE_OUT_ICI_B, B
	ld.ub	%r10,[%r4]
	ext	z80cpu_out@rm	; 	xjp.d z80cpu_out
	jp.d	z80cpu_out@rl
	sub %r3, 12			; *delay*
z80cpu_OUT_ICI_C:
	ext	0x2		; 	xld.ub %r10, [%r4+0x2]		; %a0 = r	; 	OUT_ICI_r CYCLE_OUT_ICI_C, C
	ld.ub	%r10,[%r4]
	ext	z80cpu_out@rm	; 	xjp.d z80cpu_out
	jp.d	z80cpu_out@rl
	sub %r3, 12			; *delay*
z80cpu_OUT_ICI_D:
	ext	0x5		; 	xld.ub %r10, [%r4+0x5]		; %a0 = r	; 	OUT_ICI_r CYCLE_OUT_ICI_D, D
	ld.ub	%r10,[%r4]
	ext	z80cpu_out@rm	; 	xjp.d z80cpu_out
	jp.d	z80cpu_out@rl
	sub %r3, 12			; *delay*
z80cpu_OUT_ICI_E:
	ext	0x4		; 	xld.ub %r10, [%r4+0x4]		; %a0 = r	; 	OUT_ICI_r CYCLE_OUT_ICI_E, E
	ld.ub	%r10,[%r4]
	ext	z80cpu_out@rm	; 	xjp.d z80cpu_out
	jp.d	z80cpu_out@rl
	sub %r3, 12			; *delay*
z80cpu_OUT_ICI_H:
	ext	0x7		; 	xld.ub %r10, [%r4+0x7]		; %a0 = r	; 	OUT_ICI_r CYCLE_OUT_ICI_H, H
	ld.ub	%r10,[%r4]
	ext	z80cpu_out@rm	; 	xjp.d z80cpu_out
	jp.d	z80cpu_out@rl
	sub %r3, 12			; *delay*
z80cpu_OUT_ICI_L:
	ext	0x6		; 	xld.ub %r10, [%r4+0x6]		; %a0 = r	; 	OUT_ICI_r CYCLE_OUT_ICI_L, L
	ld.ub	%r10,[%r4]
	ext	z80cpu_out@rm	; 	xjp.d z80cpu_out
	jp.d	z80cpu_out@rl
	sub %r3, 12			; *delay*

;
;	Condition Bits Affected: None
;
z80cpu_OUT_InI_A:
	ext	0x28		; 	xld.w  %r11, [%r4+0x28]		; %r11 = OUT
	ld.w	%r11,[%r4]
	ld.ub  %r12, [%r2]+		; %r12 = n
	ld.w   %r13, %r0			; %r12 = n|A<<8
	sll	%r13,0x8	; 	xsll   %r13, 8			; (アドレスバスのbit15-8にはAレジスタの値が出力されます)
	or     %r12, %r13
	call.d %r11			; OUT (n|A<<8), A
	ld.w   %r13, %r0			; %r13 = A *delay*
	ext	z80cpu+0x0@h	; 	xld.w  %r4, z80cpu		; %r4復元
	ext	z80cpu+0x0@m
	ld.w	%r4,z80cpu+0x0@l
	ext	z80mem+0x0@h	; 	xld.w  %r5, z80mem		; %r5復元
	ext	z80mem+0x0@m
	ld.w	%r5,z80mem+0x0@l
	ret.d
	sub %r3, 11	; *delay*

;----------------------------------------------------------------------------

;
;	S	is unknown
;	Z	is set if B-1 is 0, reset otherwise
;	H	is unknown
;	P/V	is unknown
;	N	is set
;	C	is not affected
;
; [note]
;	* フラグ変化は"DEC B"に等価です。
;
z80cpu_OUTI:
	ext	0x6		; 	xld.uh %r6, [%r4+0x6]		; %s0 = HL
	ld.uh	%r6,[%r4]
	add    %r6, %r5		; %s0 = mem+HL
	ld.ub  %r10, [%r6]+		; %a0 = [mem+HL], %s0 = mem+HL+1
	ext	z80cpu_out@rm	; 	xcall.d z80cpu_out		; OUT (C), [mem+HL]
	call.d	z80cpu_out@rl
	sub    %r6, %r5		; %s0 = HL+1 *delay*
	ext	0x6		; 	xld.h [%r4+0x6], %r6		; HL = HL+1
	ld.h	[%r4],%r6
	;
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = B
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8		; %a0 = B-1
	call	z80cpu_dec8@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; B = B-1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 16		; *delay*

;
;	S	is unknown
;	Z	is set
;	H	is unknown
;	P/V	is unknown
;	N	is set
;	C	is not affected
;
; [note]
;	* B-1==0の場合、OTIRの消費サイクル数はOUTIと同じです。
;	  従って、OTIRの中でCycleを減らす必要はありません。
;	* B-1!=0の場合、OTIRの消費サイクル数はOUTI+5です。
;	  OTIR命令を繰り返すために、自身の2バイト分戻ります。
;
z80cpu_OTIR:
	call	z80cpu_OUTI	; 	xcall z80cpu_OUTI		; OUTI
	ext	0x2		; 	xand %r9, %r1, 0x02
	and	%r9,%r1
	jrne 3
	sub  %r2, 2			; (skip?)
	sub  %r3, 5			; (skip?)
	ret

;
;	S	is unknown
;	Z	is set if B-1 is 0, reset otherwise
;	H	is unknown
;	P/V	is unknown
;	N	is set
;	C	is not affected
;
; [note]
;	* フラグ変化は"DEC B"に等価です。
;
z80cpu_OUTD:
	ext	0x6		; 	xld.uh %r6, [%r4+0x6]		; %s0 = HL
	ld.uh	%r6,[%r4]
	add    %r6, %r5		; %s0 = mem+HL
	ld.ub  %r10, [%r6]		; %a0 = [mem+HL]
	sub    %r6, 1			; %s0 = mem+HL-1
	ext	z80cpu_out@rm	; 	xcall.d z80cpu_out		; OUT (C), [mem+HL]
	call.d	z80cpu_out@rl
	sub    %r6, %r5		; %s0 = HL-1 *delay*
	ext	0x6		; 	xld.h [%r4+0x6], %r6		; HL = HL-1
	ld.h	[%r4],%r6
	;
	ext	0x3		; 	xld.ub %r10, [%r4+0x3]		; %a0 = B
	ld.ub	%r10,[%r4]
	ext	z80cpu_dec8@rm	; 	xcall z80cpu_dec8		; %a0 = B-1
	call	z80cpu_dec8@rl
	ext	0x3		; 	xld.b [%r4+0x3], %r10		; B = B-1
	ld.b	[%r4],%r10
	ret.d
	sub %r3, 16		; *delay*

;
;	S	is unknown
;	Z	is set
;	H	is unknown
;	P/V	is unknown
;	N	is set
;	C	is not affected
;
; [note]
;	* B-1==0の場合、OTDRの消費サイクル数はOUTDと同じです。
;	  従って、OTDRの中でCycleを減らす必要はありません。
;	* B-1!=0の場合、OTDRの消費サイクル数はOUTD+5です。
;	  OTDR命令を繰り返すために、自身の2バイト分戻ります。
;
z80cpu_OTDR:
	call	z80cpu_OUTD	; 	xcall z80cpu_OUTD		; OUTD
	ext	0x2		; 	xand %r9, %r1, 0x02
	and	%r9,%r1
	jrne 3
	sub  %r2, 2			; (skip?)
	sub  %r3, 5			; (skip?)
	ret

;****************************************************************************
;	
;****************************************************************************
