;
;	clipz8ca.h
;
;	P/ECE Z80 Emulator (高速版)
;
;	CLiP - Common Library for P/ECE
;	Copyright (C) 2001-2005 Naoyuki Sawa
;
;	* Mon Jan 10 19:00:00 JST 2005 Naoyuki Sawa
;	- 作成開始。
;

; clipz8ca.s、framz8ca.sにインクルードして使います。

;****************************************************************************
;	Z80CPU構造体
;****************************************************************************

; 通常、レジスタに保持するフィールドは、"_.._"というシンボルにしてあります。
; うっかり読み書きして、保持している値との不整合が発生するのを防ぐためです。
				; /*typedef*/ struct _Z80CPU {
#define _AF_		 0	; unsigned short af;		/* + 0,2 */
#define BC		 2	; unsigned short bc;		/* + 2,2 */
#define DE		 4	; unsigned short de;		/* + 4,2 */
#define HL		 6	; unsigned short hl;		/* + 6,2 */
#define AF2		 8	; unsigned short af2;		/* + 8,2 */
#define BC2		10	; unsigned short bc2;		/* +10,2 */
#define DE2		12	; unsigned short de2;		/* +12,2 */
#define HL2		14	; unsigned short hl2;		/* +14,2 */
#define IX		16	; unsigned short ix;		/* +16,2 */
#define IY		18	; unsigned short iy;		/* +18,2 */
#define SP		20	; unsigned short sp;		/* +20,2 */
#define _PC_		22	; unsigned short pc;		/* +22,2 */
#define R		24	; unsigned char r;		/* +24,1 */
#define I		25	; unsigned char i;		/* +25,1 */
#define IM		26	; unsigned char im;		/* +26,1 */
#define IFF1		27	; unsigned char iff1;		/* +27,1 */
#define IFF2		28	; unsigned char iff2;		/* +28,1 */
#define HALT		29	; unsigned char halt;		/* +29,1 */
#define PENDING		30	; unsigned char pending;	/* +30,1 */
#define PENDING_NO	31	; unsigned char pending_no;	/* +31,1 */
#define _CYCLE_		32	; cycle;			/* +32,4 */
#define IN		36	; Z80CPUIN* in;			/* +36,4 */
#define OUT		40	; Z80CPUOUT* out;		/* +40,4 */
#define SIZEOF_Z80CPU	44	; } /*Z80CPU*/;			/* =44   */

#define _F_		 0
#define _A_		 1
#define C		 2
#define B		 3
#define E		 4
#define D		 5
#define L		 6
#define H		 7
#define IXL		16
#define IXH		17
#define IYL		18
#define IYH		19

;****************************************************************************
;	レジスタ割り当て
;****************************************************************************

#define A		r0	; Aレジスタを保持。              [31:8]は常に0。
#define F		r1	; Fレジスタを(NHCPZS)形式で保持。[31:6]は常に0。
#define PC		r2	; PCレジスタを(&z80mem[PC])形式で保持。
#define CYCLE		r3	; 残りCycle数を保持。
#define CPU		r4	; z80cpuの先頭アドレスに固定。
#define MEM		r5	; z80memの先頭アドレスに固定。
#define s0		r6	; 命令ルーチンにて使用。サブルーチンは値を維持する。
#define s1		r7	; 命令ルーチンにて使用。サブルーチンは値を維持する。
;			r8	; ゼロレジスタ。      (P/ECE仕様)
;			r9	; スクラッチレジスタ。(S1C33仕様)
#define a0		r10	; 命令ルーチンからサブルーチンへの第一引数／サブルーチンからの戻り値。戻り値が無い場合、サブルーチンは値を破壊する。
#define a1		r11	; 命令ルーチンからサブルーチンへの第二引数／サブルーチンからの戻り値。戻り値が無い場合、サブルーチンは値を破壊する。
#define t0		r12	; 命令ルーチンおよびサブルーチンにて使用。サブルーチンは値を破壊する。
#define t1		r13	; 命令ルーチンおよびサブルーチンにて使用。サブルーチンは値を破壊する。
#define t2		r14	; 命令ルーチンおよびサブルーチンにて使用。サブルーチンは値を破壊する。
#define t3		r15	; 命令ルーチンおよびサブルーチンにて使用。サブルーチンは値を破壊する。

;****************************************************************************
;	フラグビット定義
;****************************************************************************

; * %rFレジスタのフラグビットです。すなわち、F(NHCPZS)の並びです。
; - アルファベット2文字のフラグ名称は、"Undocumented Z80"から借用しました。
#define SF	0x01
#define ZF	0x02
#define PF	0x04
#define CF	0x08
#define HF	0x10
#define NF	0x20

;****************************************************************************
;	8-Bit Load Group
;****************************************************************************

#define CYCLE_LD_A_n		7
#define CYCLE_LD_A_A		4
#define CYCLE_LD_A_B		4
#define CYCLE_LD_A_C		4
#define CYCLE_LD_A_D		4
#define CYCLE_LD_A_E		4
#define CYCLE_LD_A_H		4
#define CYCLE_LD_A_L		4
#define CYCLE_LD_A_IXH		8
#define CYCLE_LD_A_IXL		8
#define CYCLE_LD_A_IYH		8
#define CYCLE_LD_A_IYL		8
#define CYCLE_LD_B_n		7
#define CYCLE_LD_B_A		4
#define CYCLE_LD_B_B		4
#define CYCLE_LD_B_C		4
#define CYCLE_LD_B_D		4
#define CYCLE_LD_B_E		4
#define CYCLE_LD_B_H		4
#define CYCLE_LD_B_L		4
#define CYCLE_LD_B_IXH		8
#define CYCLE_LD_B_IXL		8
#define CYCLE_LD_B_IYH		8
#define CYCLE_LD_B_IYL		8
#define CYCLE_LD_C_n		7
#define CYCLE_LD_C_A		4
#define CYCLE_LD_C_B		4
#define CYCLE_LD_C_C		4
#define CYCLE_LD_C_D		4
#define CYCLE_LD_C_E		4
#define CYCLE_LD_C_H		4
#define CYCLE_LD_C_L		4
#define CYCLE_LD_C_IXH		8
#define CYCLE_LD_C_IXL		8
#define CYCLE_LD_C_IYH		8
#define CYCLE_LD_C_IYL		8
#define CYCLE_LD_D_n		7
#define CYCLE_LD_D_A		4
#define CYCLE_LD_D_B		4
#define CYCLE_LD_D_C		4
#define CYCLE_LD_D_D		4
#define CYCLE_LD_D_E		4
#define CYCLE_LD_D_H		4
#define CYCLE_LD_D_L		4
#define CYCLE_LD_D_IXH		8
#define CYCLE_LD_D_IXL		8
#define CYCLE_LD_D_IYH		8
#define CYCLE_LD_D_IYL		8
#define CYCLE_LD_E_n		7
#define CYCLE_LD_E_A		4
#define CYCLE_LD_E_B		4
#define CYCLE_LD_E_C		4
#define CYCLE_LD_E_D		4
#define CYCLE_LD_E_E		4
#define CYCLE_LD_E_H		4
#define CYCLE_LD_E_L		4
#define CYCLE_LD_E_IXH		8
#define CYCLE_LD_E_IXL		8
#define CYCLE_LD_E_IYH		8
#define CYCLE_LD_E_IYL		8
#define CYCLE_LD_H_n		7
#define CYCLE_LD_H_A		4
#define CYCLE_LD_H_B		4
#define CYCLE_LD_H_C		4
#define CYCLE_LD_H_D		4
#define CYCLE_LD_H_E		4
#define CYCLE_LD_H_H		4
#define CYCLE_LD_H_L		4
#define CYCLE_LD_L_n		7
#define CYCLE_LD_L_A		4
#define CYCLE_LD_L_B		4
#define CYCLE_LD_L_C		4
#define CYCLE_LD_L_D		4
#define CYCLE_LD_L_E		4
#define CYCLE_LD_L_H		4
#define CYCLE_LD_L_L		4
#define CYCLE_LD_IXH_n		11
#define CYCLE_LD_IXH_A		8
#define CYCLE_LD_IXH_B		8
#define CYCLE_LD_IXH_C		8
#define CYCLE_LD_IXH_D		8
#define CYCLE_LD_IXH_E		8
#define CYCLE_LD_IXH_IXH	8
#define CYCLE_LD_IXH_IXL	8
#define CYCLE_LD_IXL_n		11
#define CYCLE_LD_IXL_A		8
#define CYCLE_LD_IXL_B		8
#define CYCLE_LD_IXL_C		8
#define CYCLE_LD_IXL_D		8
#define CYCLE_LD_IXL_E		8
#define CYCLE_LD_IXL_IXH	8
#define CYCLE_LD_IXL_IXL	8
#define CYCLE_LD_IYH_n		11
#define CYCLE_LD_IYH_A		8
#define CYCLE_LD_IYH_B		8
#define CYCLE_LD_IYH_C		8
#define CYCLE_LD_IYH_D		8
#define CYCLE_LD_IYH_E		8
#define CYCLE_LD_IYH_IYH	8
#define CYCLE_LD_IYH_IYL	8
#define CYCLE_LD_IYL_n		11
#define CYCLE_LD_IYL_A		8
#define CYCLE_LD_IYL_B		8
#define CYCLE_LD_IYL_C		8
#define CYCLE_LD_IYL_D		8
#define CYCLE_LD_IYL_E		8
#define CYCLE_LD_IYL_IYH	8
#define CYCLE_LD_IYL_IYL	8

#define CYCLE_LD_A_IlmI		13
#define CYCLE_LD_A_IBCI		7
#define CYCLE_LD_A_IDEI		7
#define CYCLE_LD_A_IHLI		7
#define CYCLE_LD_B_IHLI		7
#define CYCLE_LD_C_IHLI		7
#define CYCLE_LD_D_IHLI		7
#define CYCLE_LD_E_IHLI		7
#define CYCLE_LD_H_IHLI		7
#define CYCLE_LD_L_IHLI		7
#define CYCLE_LD_A_IIX_dI	19
#define CYCLE_LD_B_IIX_dI	19
#define CYCLE_LD_C_IIX_dI	19
#define CYCLE_LD_D_IIX_dI	19
#define CYCLE_LD_E_IIX_dI	19
#define CYCLE_LD_H_IIX_dI	19
#define CYCLE_LD_L_IIX_dI	19
#define CYCLE_LD_A_IIY_dI	19
#define CYCLE_LD_B_IIY_dI	19
#define CYCLE_LD_C_IIY_dI	19
#define CYCLE_LD_D_IIY_dI	19
#define CYCLE_LD_E_IIY_dI	19
#define CYCLE_LD_H_IIY_dI	19
#define CYCLE_LD_L_IIY_dI	19

#define CYCLE_LD_IlmI_A		13
#define CYCLE_LD_IHLI_n		10
#define CYCLE_LD_IBCI_A		7
#define CYCLE_LD_IDEI_A		7
#define CYCLE_LD_IHLI_A		7
#define CYCLE_LD_IHLI_B		7
#define CYCLE_LD_IHLI_C		7
#define CYCLE_LD_IHLI_D		7
#define CYCLE_LD_IHLI_E		7
#define CYCLE_LD_IHLI_H		7
#define CYCLE_LD_IHLI_L		7
#define CYCLE_LD_IIX_dI_n	19
#define CYCLE_LD_IIY_dI_n	19
#define CYCLE_LD_IIX_dI_A	19
#define CYCLE_LD_IIX_dI_B	19
#define CYCLE_LD_IIX_dI_C	19
#define CYCLE_LD_IIX_dI_D	19
#define CYCLE_LD_IIX_dI_E	19
#define CYCLE_LD_IIX_dI_H	19
#define CYCLE_LD_IIX_dI_L	19
#define CYCLE_LD_IIY_dI_A	19
#define CYCLE_LD_IIY_dI_B	19
#define CYCLE_LD_IIY_dI_C	19
#define CYCLE_LD_IIY_dI_D	19
#define CYCLE_LD_IIY_dI_E	19
#define CYCLE_LD_IIY_dI_H	19
#define CYCLE_LD_IIY_dI_L	19

#define CYCLE_LD_A_I		9
#define CYCLE_LD_A_R		9
#define CYCLE_LD_I_A		9
#define CYCLE_LD_R_A		9

;****************************************************************************
;	16-Bit Load Group
;****************************************************************************

#define CYCLE_LD_SP_HL		6
#define CYCLE_LD_SP_IX		10
#define CYCLE_LD_SP_IY		10

#define CYCLE_LD_BC_lm		10
#define CYCLE_LD_DE_lm		10
#define CYCLE_LD_HL_lm		10
#define CYCLE_LD_SP_lm		10
#define CYCLE_LD_IX_lm		14
#define CYCLE_LD_IY_lm		14

#define CYCLE_LD_BC_IlmI	20
#define CYCLE_LD_DE_IlmI	20
#define CYCLE_LD_HL_IlmI	16
#define CYCLE_LD_SP_IlmI	20
#define CYCLE_LD_IX_IlmI	20
#define CYCLE_LD_IY_IlmI	20

#define CYCLE_LD_IlmI_BC	20
#define CYCLE_LD_IlmI_DE	20
#define CYCLE_LD_IlmI_HL	16
#define CYCLE_LD_IlmI_SP	20
#define CYCLE_LD_IlmI_IX	20
#define CYCLE_LD_IlmI_IY	20

#define CYCLE_POP_AF		10
#define CYCLE_POP_BC		10
#define CYCLE_POP_DE		10
#define CYCLE_POP_HL		10
#define CYCLE_POP_IX		14
#define CYCLE_POP_IY		14

#define CYCLE_PUSH_AF		11
#define CYCLE_PUSH_BC		11
#define CYCLE_PUSH_DE		11
#define CYCLE_PUSH_HL		11
#define CYCLE_PUSH_IX		15
#define CYCLE_PUSH_IY		15

;****************************************************************************
;	Exchange, Block Transfer, and Search Group
;****************************************************************************

#define CYCLE_EX_ISPI_HL	19
#define CYCLE_EX_ISPI_IX	23
#define CYCLE_EX_ISPI_IY	23
#define CYCLE_EX_AF_AF2		4
#define CYCLE_EX_DE_HL		4
#define CYCLE_EXX		4

#define CYCLE_LDI		16
#define CYCLE_LDIR		16
#define CYCLE_LDD		16
#define CYCLE_LDDR		16

#define CYCLE_CPI		16
#define CYCLE_CPIR		16
#define CYCLE_CPD		16
#define CYCLE_CPDR		16

;****************************************************************************
;	8-Bit Arithmetic Group
;****************************************************************************

#define CYCLE_ADD_A_n		7
#define CYCLE_ADD_A_A		4
#define CYCLE_ADD_A_B		4
#define CYCLE_ADD_A_C		4
#define CYCLE_ADD_A_D		4
#define CYCLE_ADD_A_E		4
#define CYCLE_ADD_A_H		4
#define CYCLE_ADD_A_L		4
#define CYCLE_ADD_A_IXH		8
#define CYCLE_ADD_A_IXL		8
#define CYCLE_ADD_A_IYH		8
#define CYCLE_ADD_A_IYL		8
#define CYCLE_ADD_A_IHLI	7
#define CYCLE_ADD_A_IIX_dI	19
#define CYCLE_ADD_A_IIY_dI	19

#define CYCLE_ADC_A_n		7
#define CYCLE_ADC_A_A		4
#define CYCLE_ADC_A_B		4
#define CYCLE_ADC_A_C		4
#define CYCLE_ADC_A_D		4
#define CYCLE_ADC_A_E		4
#define CYCLE_ADC_A_H		4
#define CYCLE_ADC_A_L		4
#define CYCLE_ADC_A_IXH		8
#define CYCLE_ADC_A_IXL		8
#define CYCLE_ADC_A_IYH		8
#define CYCLE_ADC_A_IYL		8
#define CYCLE_ADC_A_IHLI	7
#define CYCLE_ADC_A_IIX_dI	19
#define CYCLE_ADC_A_IIY_dI	19

#define CYCLE_SUB_n		7
#define CYCLE_SUB_A		4
#define CYCLE_SUB_B		4
#define CYCLE_SUB_C		4
#define CYCLE_SUB_D		4
#define CYCLE_SUB_E		4
#define CYCLE_SUB_H		4
#define CYCLE_SUB_L		4
#define CYCLE_SUB_IXH		8
#define CYCLE_SUB_IXL		8
#define CYCLE_SUB_IYH		8
#define CYCLE_SUB_IYL		8
#define CYCLE_SUB_IHLI		7
#define CYCLE_SUB_IIX_dI	19
#define CYCLE_SUB_IIY_dI	19

#define CYCLE_SBC_A_n		7
#define CYCLE_SBC_A_A		4
#define CYCLE_SBC_A_B		4
#define CYCLE_SBC_A_C		4
#define CYCLE_SBC_A_D		4
#define CYCLE_SBC_A_E		4
#define CYCLE_SBC_A_H		4
#define CYCLE_SBC_A_L		4
#define CYCLE_SBC_A_IXH		8
#define CYCLE_SBC_A_IXL		8
#define CYCLE_SBC_A_IYH		8
#define CYCLE_SBC_A_IYL		8
#define CYCLE_SBC_A_IHLI	7
#define CYCLE_SBC_A_IIX_dI	19
#define CYCLE_SBC_A_IIY_dI	19

#define CYCLE_AND_n		7
#define CYCLE_AND_A		4
#define CYCLE_AND_B		4
#define CYCLE_AND_C		4
#define CYCLE_AND_D		4
#define CYCLE_AND_E		4
#define CYCLE_AND_H		4
#define CYCLE_AND_L		4
#define CYCLE_AND_IXH		8
#define CYCLE_AND_IXL		8
#define CYCLE_AND_IYH		8
#define CYCLE_AND_IYL		8
#define CYCLE_AND_IHLI		7
#define CYCLE_AND_IIX_dI	19
#define CYCLE_AND_IIY_dI	19

#define CYCLE_OR_n		7
#define CYCLE_OR_A		4
#define CYCLE_OR_B		4
#define CYCLE_OR_C		4
#define CYCLE_OR_D		4
#define CYCLE_OR_E		4
#define CYCLE_OR_H		4
#define CYCLE_OR_L		4
#define CYCLE_OR_IXH		8
#define CYCLE_OR_IXL		8
#define CYCLE_OR_IYH		8
#define CYCLE_OR_IYL		8
#define CYCLE_OR_IHLI		7
#define CYCLE_OR_IIX_dI		19
#define CYCLE_OR_IIY_dI		19

#define CYCLE_XOR_n		7
#define CYCLE_XOR_A		4
#define CYCLE_XOR_B		4
#define CYCLE_XOR_C		4
#define CYCLE_XOR_D		4
#define CYCLE_XOR_E		4
#define CYCLE_XOR_H		4
#define CYCLE_XOR_L		4
#define CYCLE_XOR_IXH		8
#define CYCLE_XOR_IXL		8
#define CYCLE_XOR_IYH		8
#define CYCLE_XOR_IYL		8
#define CYCLE_XOR_IHLI		7
#define CYCLE_XOR_IIX_dI	19
#define CYCLE_XOR_IIY_dI	19

#define CYCLE_CP_n		7
#define CYCLE_CP_A		4
#define CYCLE_CP_B		4
#define CYCLE_CP_C		4
#define CYCLE_CP_D		4
#define CYCLE_CP_E		4
#define CYCLE_CP_H		4
#define CYCLE_CP_L		4
#define CYCLE_CP_IXH		8
#define CYCLE_CP_IXL		8
#define CYCLE_CP_IYH		8
#define CYCLE_CP_IYL		8
#define CYCLE_CP_IHLI		7
#define CYCLE_CP_IIX_dI		19
#define CYCLE_CP_IIY_dI		19

#define CYCLE_INC_A		4
#define CYCLE_INC_B		4
#define CYCLE_INC_C		4
#define CYCLE_INC_D		4
#define CYCLE_INC_E		4
#define CYCLE_INC_H		4
#define CYCLE_INC_L		4
#define CYCLE_INC_IXH		8
#define CYCLE_INC_IXL		8
#define CYCLE_INC_IYH		8
#define CYCLE_INC_IYL		8
#define CYCLE_INC_IHLI		11
#define CYCLE_INC_IIX_dI	23
#define CYCLE_INC_IIY_dI	23

#define CYCLE_DEC_A		4
#define CYCLE_DEC_B		4
#define CYCLE_DEC_C		4
#define CYCLE_DEC_D		4
#define CYCLE_DEC_E		4
#define CYCLE_DEC_H		4
#define CYCLE_DEC_L		4
#define CYCLE_DEC_IXH		8
#define CYCLE_DEC_IXL		8
#define CYCLE_DEC_IYH		8
#define CYCLE_DEC_IYL		8
#define CYCLE_DEC_IHLI		11
#define CYCLE_DEC_IIX_dI	23
#define CYCLE_DEC_IIY_dI	23

;****************************************************************************
;	General-Purpose Arithmetic and CPU Control Group
;****************************************************************************

#define CYCLE_DAA		4
#define CYCLE_CPL		4
#define CYCLE_NEG		8
#define CYCLE_CCF		4
#define CYCLE_SCF		4
#define CYCLE_NOP		4
#define CYCLE_HALT		4
#define CYCLE_DI		4
#define CYCLE_EI		4
#define CYCLE_IM_0		8
#define CYCLE_IM_1		8
#define CYCLE_IM_2		8

;****************************************************************************
;	16-Bit Arithmetic Group
;****************************************************************************

#define CYCLE_ADD_HL_BC		11
#define CYCLE_ADD_HL_DE		11
#define CYCLE_ADD_HL_HL		11
#define CYCLE_ADD_HL_SP		11
#define CYCLE_ADD_IX_BC		15
#define CYCLE_ADD_IX_DE		15
#define CYCLE_ADD_IX_IX		15
#define CYCLE_ADD_IX_SP		15
#define CYCLE_ADD_IY_BC		15
#define CYCLE_ADD_IY_DE		15
#define CYCLE_ADD_IY_IY		15
#define CYCLE_ADD_IY_SP		15

#define CYCLE_ADC_HL_BC		15
#define CYCLE_ADC_HL_DE		15
#define CYCLE_ADC_HL_HL		15
#define CYCLE_ADC_HL_SP		15

#define CYCLE_SBC_HL_BC		15
#define CYCLE_SBC_HL_DE		15
#define CYCLE_SBC_HL_HL		15
#define CYCLE_SBC_HL_SP		15

#define CYCLE_INC_BC		6
#define CYCLE_INC_DE		6
#define CYCLE_INC_HL		6
#define CYCLE_INC_SP		6
#define CYCLE_INC_IX		10
#define CYCLE_INC_IY		10

#define CYCLE_DEC_BC		6
#define CYCLE_DEC_DE		6
#define CYCLE_DEC_HL		6
#define CYCLE_DEC_SP		6
#define CYCLE_DEC_IX		10
#define CYCLE_DEC_IY		10

;****************************************************************************
;	Rotate and Shift Group
;****************************************************************************

#define CYCLE_RLA		4
#define CYCLE_RLCA		4
#define CYCLE_RRA		4
#define CYCLE_RRCA		4

#define CYCLE_RL_A		8
#define CYCLE_RL_B		8
#define CYCLE_RL_C		8
#define CYCLE_RL_D		8
#define CYCLE_RL_E		8
#define CYCLE_RL_H		8
#define CYCLE_RL_L		8
#define CYCLE_RL_IHLI		15
#define CYCLE_RL_IaddrI		23

#define CYCLE_RLC_A		8
#define CYCLE_RLC_B		8
#define CYCLE_RLC_C		8
#define CYCLE_RLC_D		8
#define CYCLE_RLC_E		8
#define CYCLE_RLC_H		8
#define CYCLE_RLC_L		8
#define CYCLE_RLC_IHLI		15
#define CYCLE_RLC_IaddrI	23

#define CYCLE_RR_A		8
#define CYCLE_RR_B		8
#define CYCLE_RR_C		8
#define CYCLE_RR_D		8
#define CYCLE_RR_E		8
#define CYCLE_RR_H		8
#define CYCLE_RR_L		8
#define CYCLE_RR_IHLI		15
#define CYCLE_RR_IaddrI		23

#define CYCLE_RRC_A		8
#define CYCLE_RRC_B		8
#define CYCLE_RRC_C		8
#define CYCLE_RRC_D		8
#define CYCLE_RRC_E		8
#define CYCLE_RRC_H		8
#define CYCLE_RRC_L		8
#define CYCLE_RRC_IHLI		15
#define CYCLE_RRC_IaddrI	23

#define CYCLE_SLA_A		8
#define CYCLE_SLA_B		8
#define CYCLE_SLA_C		8
#define CYCLE_SLA_D		8
#define CYCLE_SLA_E		8
#define CYCLE_SLA_H		8
#define CYCLE_SLA_L		8
#define CYCLE_SLA_IHLI		15
#define CYCLE_SLA_IaddrI	23

#define CYCLE_SRA_A		8
#define CYCLE_SRA_B		8
#define CYCLE_SRA_C		8
#define CYCLE_SRA_D		8
#define CYCLE_SRA_E		8
#define CYCLE_SRA_H		8
#define CYCLE_SRA_L		8
#define CYCLE_SRA_IHLI		15
#define CYCLE_SRA_IaddrI	23

#define CYCLE_SRL_A		8
#define CYCLE_SRL_B		8
#define CYCLE_SRL_C		8
#define CYCLE_SRL_D		8
#define CYCLE_SRL_E		8
#define CYCLE_SRL_H		8
#define CYCLE_SRL_L		8
#define CYCLE_SRL_IHLI		15
#define CYCLE_SRL_IaddrI	23

#define CYCLE_RLD		18
#define CYCLE_RRD		18

;****************************************************************************
;	Bit Set, Reset, and Test Group
;****************************************************************************

#define CYCLE_BIT_0_A		8
#define CYCLE_BIT_0_B		8
#define CYCLE_BIT_0_C		8
#define CYCLE_BIT_0_D		8
#define CYCLE_BIT_0_E		8
#define CYCLE_BIT_0_H		8
#define CYCLE_BIT_0_L		8
#define CYCLE_BIT_0_IHLI	12
#define CYCLE_BIT_0_IaddrI	20
#define CYCLE_BIT_1_A		8
#define CYCLE_BIT_1_B		8
#define CYCLE_BIT_1_C		8
#define CYCLE_BIT_1_D		8
#define CYCLE_BIT_1_E		8
#define CYCLE_BIT_1_H		8
#define CYCLE_BIT_1_L		8
#define CYCLE_BIT_1_IHLI	12
#define CYCLE_BIT_1_IaddrI	20
#define CYCLE_BIT_2_A		8
#define CYCLE_BIT_2_B		8
#define CYCLE_BIT_2_C		8
#define CYCLE_BIT_2_D		8
#define CYCLE_BIT_2_E		8
#define CYCLE_BIT_2_H		8
#define CYCLE_BIT_2_L		8
#define CYCLE_BIT_2_IHLI	12
#define CYCLE_BIT_2_IaddrI	20
#define CYCLE_BIT_3_A		8
#define CYCLE_BIT_3_B		8
#define CYCLE_BIT_3_C		8
#define CYCLE_BIT_3_D		8
#define CYCLE_BIT_3_E		8
#define CYCLE_BIT_3_H		8
#define CYCLE_BIT_3_L		8
#define CYCLE_BIT_3_IHLI	12
#define CYCLE_BIT_3_IaddrI	20
#define CYCLE_BIT_4_A		8
#define CYCLE_BIT_4_B		8
#define CYCLE_BIT_4_C		8
#define CYCLE_BIT_4_D		8
#define CYCLE_BIT_4_E		8
#define CYCLE_BIT_4_H		8
#define CYCLE_BIT_4_L		8
#define CYCLE_BIT_4_IHLI	12
#define CYCLE_BIT_4_IaddrI	20
#define CYCLE_BIT_5_A		8
#define CYCLE_BIT_5_B		8
#define CYCLE_BIT_5_C		8
#define CYCLE_BIT_5_D		8
#define CYCLE_BIT_5_E		8
#define CYCLE_BIT_5_H		8
#define CYCLE_BIT_5_L		8
#define CYCLE_BIT_5_IHLI	12
#define CYCLE_BIT_5_IaddrI	20
#define CYCLE_BIT_6_A		8
#define CYCLE_BIT_6_B		8
#define CYCLE_BIT_6_C		8
#define CYCLE_BIT_6_D		8
#define CYCLE_BIT_6_E		8
#define CYCLE_BIT_6_H		8
#define CYCLE_BIT_6_L		8
#define CYCLE_BIT_6_IHLI	12
#define CYCLE_BIT_6_IaddrI	20
#define CYCLE_BIT_7_A		8
#define CYCLE_BIT_7_B		8
#define CYCLE_BIT_7_C		8
#define CYCLE_BIT_7_D		8
#define CYCLE_BIT_7_E		8
#define CYCLE_BIT_7_H		8
#define CYCLE_BIT_7_L		8
#define CYCLE_BIT_7_IHLI	12
#define CYCLE_BIT_7_IaddrI	20

#define CYCLE_SET_0_A		8
#define CYCLE_SET_0_B		8
#define CYCLE_SET_0_C		8
#define CYCLE_SET_0_D		8
#define CYCLE_SET_0_E		8
#define CYCLE_SET_0_H		8
#define CYCLE_SET_0_L		8
#define CYCLE_SET_0_IHLI	15
#define CYCLE_SET_0_IaddrI	23
#define CYCLE_SET_1_A		8
#define CYCLE_SET_1_B		8
#define CYCLE_SET_1_C		8
#define CYCLE_SET_1_D		8
#define CYCLE_SET_1_E		8
#define CYCLE_SET_1_H		8
#define CYCLE_SET_1_L		8
#define CYCLE_SET_1_IHLI	15
#define CYCLE_SET_1_IaddrI	23
#define CYCLE_SET_2_A		8
#define CYCLE_SET_2_B		8
#define CYCLE_SET_2_C		8
#define CYCLE_SET_2_D		8
#define CYCLE_SET_2_E		8
#define CYCLE_SET_2_H		8
#define CYCLE_SET_2_L		8
#define CYCLE_SET_2_IHLI	15
#define CYCLE_SET_2_IaddrI	23
#define CYCLE_SET_3_A		8
#define CYCLE_SET_3_B		8
#define CYCLE_SET_3_C		8
#define CYCLE_SET_3_D		8
#define CYCLE_SET_3_E		8
#define CYCLE_SET_3_H		8
#define CYCLE_SET_3_L		8
#define CYCLE_SET_3_IHLI	15
#define CYCLE_SET_3_IaddrI	23
#define CYCLE_SET_4_A		8
#define CYCLE_SET_4_B		8
#define CYCLE_SET_4_C		8
#define CYCLE_SET_4_D		8
#define CYCLE_SET_4_E		8
#define CYCLE_SET_4_H		8
#define CYCLE_SET_4_L		8
#define CYCLE_SET_4_IHLI	15
#define CYCLE_SET_4_IaddrI	23
#define CYCLE_SET_5_A		8
#define CYCLE_SET_5_B		8
#define CYCLE_SET_5_C		8
#define CYCLE_SET_5_D		8
#define CYCLE_SET_5_E		8
#define CYCLE_SET_5_H		8
#define CYCLE_SET_5_L		8
#define CYCLE_SET_5_IHLI	15
#define CYCLE_SET_5_IaddrI	23
#define CYCLE_SET_6_A		8
#define CYCLE_SET_6_B		8
#define CYCLE_SET_6_C		8
#define CYCLE_SET_6_D		8
#define CYCLE_SET_6_E		8
#define CYCLE_SET_6_H		8
#define CYCLE_SET_6_L		8
#define CYCLE_SET_6_IHLI	15
#define CYCLE_SET_6_IaddrI	23
#define CYCLE_SET_7_A		8
#define CYCLE_SET_7_B		8
#define CYCLE_SET_7_C		8
#define CYCLE_SET_7_D		8
#define CYCLE_SET_7_E		8
#define CYCLE_SET_7_H		8
#define CYCLE_SET_7_L		8
#define CYCLE_SET_7_IHLI	15
#define CYCLE_SET_7_IaddrI	23

#define CYCLE_RES_0_A		8
#define CYCLE_RES_0_B		8
#define CYCLE_RES_0_C		8
#define CYCLE_RES_0_D		8
#define CYCLE_RES_0_E		8
#define CYCLE_RES_0_H		8
#define CYCLE_RES_0_L		8
#define CYCLE_RES_0_IHLI	15
#define CYCLE_RES_0_IaddrI	23
#define CYCLE_RES_1_A		8
#define CYCLE_RES_1_B		8
#define CYCLE_RES_1_C		8
#define CYCLE_RES_1_D		8
#define CYCLE_RES_1_E		8
#define CYCLE_RES_1_H		8
#define CYCLE_RES_1_L		8
#define CYCLE_RES_1_IHLI	15
#define CYCLE_RES_1_IaddrI	23
#define CYCLE_RES_2_A		8
#define CYCLE_RES_2_B		8
#define CYCLE_RES_2_C		8
#define CYCLE_RES_2_D		8
#define CYCLE_RES_2_E		8
#define CYCLE_RES_2_H		8
#define CYCLE_RES_2_L		8
#define CYCLE_RES_2_IHLI	15
#define CYCLE_RES_2_IaddrI	23
#define CYCLE_RES_3_A		8
#define CYCLE_RES_3_B		8
#define CYCLE_RES_3_C		8
#define CYCLE_RES_3_D		8
#define CYCLE_RES_3_E		8
#define CYCLE_RES_3_H		8
#define CYCLE_RES_3_L		8
#define CYCLE_RES_3_IHLI	15
#define CYCLE_RES_3_IaddrI	23
#define CYCLE_RES_4_A		8
#define CYCLE_RES_4_B		8
#define CYCLE_RES_4_C		8
#define CYCLE_RES_4_D		8
#define CYCLE_RES_4_E		8
#define CYCLE_RES_4_H		8
#define CYCLE_RES_4_L		8
#define CYCLE_RES_4_IHLI	15
#define CYCLE_RES_4_IaddrI	23
#define CYCLE_RES_5_A		8
#define CYCLE_RES_5_B		8
#define CYCLE_RES_5_C		8
#define CYCLE_RES_5_D		8
#define CYCLE_RES_5_E		8
#define CYCLE_RES_5_H		8
#define CYCLE_RES_5_L		8
#define CYCLE_RES_5_IHLI	15
#define CYCLE_RES_5_IaddrI	23
#define CYCLE_RES_6_A		8
#define CYCLE_RES_6_B		8
#define CYCLE_RES_6_C		8
#define CYCLE_RES_6_D		8
#define CYCLE_RES_6_E		8
#define CYCLE_RES_6_H		8
#define CYCLE_RES_6_L		8
#define CYCLE_RES_6_IHLI	15
#define CYCLE_RES_6_IaddrI	23
#define CYCLE_RES_7_A		8
#define CYCLE_RES_7_B		8
#define CYCLE_RES_7_C		8
#define CYCLE_RES_7_D		8
#define CYCLE_RES_7_E		8
#define CYCLE_RES_7_H		8
#define CYCLE_RES_7_L		8
#define CYCLE_RES_7_IHLI	15
#define CYCLE_RES_7_IaddrI	23

;****************************************************************************
;	Jump Group
;****************************************************************************

#define CYCLE_JP_IHLI		4
#define CYCLE_JP_IIXI		8
#define CYCLE_JP_IIYI		8

#define CYCLE_JP_lm		10
#define CYCLE_JP_Z_lm		10
#define CYCLE_JP_NZ_lm		10
#define CYCLE_JP_C_lm		10
#define CYCLE_JP_NC_lm		10
#define CYCLE_JP_PE_lm		10
#define CYCLE_JP_PO_lm		10
#define CYCLE_JP_M_lm		10
#define CYCLE_JP_P_lm		10

#define CYCLE_JR_e		12
#define CYCLE_JR_Z_e		7
#define CYCLE_JR_NZ_e		7
#define CYCLE_JR_C_e		7
#define CYCLE_JR_NC_e		7

#define CYCLE_DJNZ_e		8

;****************************************************************************
;	Call and Return Group
;****************************************************************************

#define CYCLE_CALL_lm		17
#define CYCLE_CALL_Z_lm		10
#define CYCLE_CALL_NZ_lm	10
#define CYCLE_CALL_C_lm		10
#define CYCLE_CALL_NC_lm	10
#define CYCLE_CALL_PE_lm	10
#define CYCLE_CALL_PO_lm	10
#define CYCLE_CALL_M_lm		10
#define CYCLE_CALL_P_lm		10

#define CYCLE_RET		10
#define CYCLE_RET_Z		5
#define CYCLE_RET_NZ		5
#define CYCLE_RET_C		5
#define CYCLE_RET_NC		5
#define CYCLE_RET_PE		5
#define CYCLE_RET_PO		5
#define CYCLE_RET_M		5
#define CYCLE_RET_P		5

#define CYCLE_RETI		14
#define CYCLE_RETN		14

#define CYCLE_RST_00H		11
#define CYCLE_RST_08H		11
#define CYCLE_RST_10H		11
#define CYCLE_RST_18H		11
#define CYCLE_RST_20H		11
#define CYCLE_RST_28H		11
#define CYCLE_RST_30H		11
#define CYCLE_RST_38H		11

;****************************************************************************
;	Input and Output Group
;****************************************************************************

#define CYCLE_IN_A_ICI		12
#define CYCLE_IN_B_ICI		12
#define CYCLE_IN_C_ICI		12
#define CYCLE_IN_D_ICI		12
#define CYCLE_IN_E_ICI		12
#define CYCLE_IN_H_ICI		12
#define CYCLE_IN_L_ICI		12
#define CYCLE_IN_A_InI		11

#define CYCLE_INI		16
#define CYCLE_INIR		16
#define CYCLE_IND		16
#define CYCLE_INDR		16

#define CYCLE_OUT_ICI_A		12
#define CYCLE_OUT_ICI_B		12
#define CYCLE_OUT_ICI_C		12
#define CYCLE_OUT_ICI_D		12
#define CYCLE_OUT_ICI_E		12
#define CYCLE_OUT_ICI_H		12
#define CYCLE_OUT_ICI_L		12
#define CYCLE_OUT_InI_A		11

#define CYCLE_OUTI		16
#define CYCLE_OTIR		16
#define CYCLE_OUTD		16
#define CYCLE_OTDR		16

;****************************************************************************
;	
;****************************************************************************
